At Synopsys, you will work directly with the semiconductor teams building the chips that power everything, and what you recommend will show up in silicon.
What You'll Be Doing
Own technical relationships with customer RTL, synthesis, formal verification, and physical design teams from flow evaluation through tapeout, serving as their trusted technical partner for Synopsys synthesis and equivalence checking products
Debug complex synthesis and Formality issues reported by customers, reproduce problems in your own environment when possible, isolate root causes, and deliver clear recommendations or escalate to R&D with well-documented test cases
Guide customers on RTL-to-netlist methodology using Fusion Compiler, Design Compiler, RTL Architect, and Formality, including advice on hierarchy, datapath optimization, physical-aware synthesis, clock gating, multi-bit registers, and handoff to place-and-route
Analyze synthesis results, timing reports, constraint files, library characterization, and PPA outcomes to explain design behavior, identify optimization opportunities, and improve correlation with downstream implementation
Create and maintain reusable scripts, reference flows, application notes, debug guides, and training materials that scale across customer programs and can be shared with global applications teams
Translate recurring customer challenges and feature requests into clear use cases and product feedback for Synopsys R&D, and validate fixes and enhancements in real customer contexts
Support technical evaluations, benchmarks, design reviews, and adoption of new synthesis and formal verification technologies across customer design teams
The Impact You Will Have
Customers will ship complex SoCs on schedule because you helped them resolve synthesis and equivalence checking issues that would have blocked tapeout
Design teams will achieve better power, performance, and area outcomes because you identified RTL, constraint, or methodology improvements they could not see on their own
Synopsys products will become more robust and easier to deploy because you brought field observations back to R&D as reproducible test cases and actionable feature requests
Customer synthesis flows will scale and stabilize across programs because you built reference methodologies, scripts, and documentation that teams can reuse without starting from scratch
Engineers at customer sites will trust Synopsys as a technical partner, not just a vendor, because you showed up during the hard problems and helped them solve it
Your colleagues across global applications, support, and product engineering teams will benefit from the knowledge you share, the materials you create, and the mentorship you provide
Synopsys will win competitive evaluations and expand deployments because customers see the value you deliver during technical engagements and benchmarks
What You'll Need
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent hands-on experience in ASIC design or EDA applications
5 or more years of hands-on experience in ASIC or SoC design, logic synthesis, formal equivalence checking, or EDA applications engineering, with at least one production design cycle or tapeout under your belt
Strong working knowledge of Verilog or SystemVerilog RTL, logic synthesis fundamentals, timing constraints (SDC), standard-cell libraries, and RTL-to-netlist design flows
Practical experience with formal equivalence checking tools, including the ability to set up comparisons, investigate setup issues, and analyze proof failures or inconclusive results
Proficiency with Tcl scripting and Linux command-line environments, you can write or modify scripts to automate flow setup, parse reports, and accelerate debug
Direct experience with Synopsys Design Compiler, Fusion Compiler, RTL Architect, or Formality is a strong plus, as is familiarity with static timing analysis tools like PrimeTime
Experience with UPF, low-power design, hierarchical SoCs, advanced process nodes, or physical-aware synthesis is valuable but not required
Who You Are
You can explain a complex synthesis tradeoff to a customer design lead in two sentences without losing the technical nuance, and you know when to stop talking and start showing data
You manage multiple customer engagements in parallel without dropping threads, you know which issue needs attention today and which one can wait until tomorrow, and you communicate status and risks clearly
You do not need perfect information to move forward, you work with incomplete constraints, messy RTL, and ambiguous requirements, and you ask the right questions to fill in the gaps
You care about the details, a missing clock uncertainty value, an incorrect case analysis, or a suboptimal hierarchy decision bothers you because you know it will cost the customer time or QoR downstream
You are comfortable saying 'I do not know yet, but I will find out' and then actually finding out, whether that means digging into tool internals, calling R&D, or building a test case from scratch
You treat customer problems like your own, if their synthesis run is failing at 2 a.m. before a Monday review, you are the kind of engineer who helps them get it working
The Team You'll Be Part Of
You will join Synopsys' Technical Sales Group, the team responsible for helping customers build high-performance silicon chips faster using our industry-leading design, verification, and implementation solutions. This is a customer-facing engineering role within the applications organization, working closely with field sales, R&D, product engineering, and global applications teams. You will support semiconductor customers across a range of design programs, from early evaluations to tapeout, and contribute to the methodologies and materials that enable successful deployments worldwide.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
