Develop and execute validation plans covering memory functionality, performance, reliability, power, and corner-case scenarios.
Lead debug of DDR controller, PHY, firmware, SI/PI, timing, and system-level issues.
Validate interactions between DDR, CPU, GPU, NPU, cache hierarchy, NoC, and system software.
Drive bandwidth, latency, QoS, memory pressure, and AI workload characterization.
Develop scalable automation, regression infrastructure, and debug analytics frameworks.
Partner with Architecture, Design, Firmware, SI/PI, Package, and DRAM vendors to root-cause and resolve issues.
Minimum Requirements
BS or MS or PhD in EE, CE, CS, or related field.
5+ years of experience in DDR/memory subsystem validation or silicon bring-up.
Strong understanding of
LPDDR4/5/5X/6 architectures
DDR controllers and PHYs
Memory training and calibration algorithms
Cache, coherency, and NoC architectures
Power management and low-power memory features
Strong post-silicon debug experience.
Proficiency in C/C++ and low-level software development.
Preferred Qualifications
Mobile SoC, AI compute, automotive, or server platform validation experience.
Familiarity with SI/PI analysis, memory performance tuning, and thermal characterization.
Experience driving first-silicon memory bring-up and volume production qualification.
Minimum Qualifications
- Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
- OR
- Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
- OR
- PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
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