Key Responsibilities
Lead DFT strategy and execution across complex SoC and MCU designs targeting AI data center and humanoid system applications
Direct and guide a team of DFT engineers in the design, development, and evaluation of test structures including scan chains, BIST, JTAG, boundary scan, and ATPG flows
Prepare and present outcomes of DFT projects, test coverage metrics, and manufacturing test results; make actionable recommendations to achieve desired results
Collaborate cross-functionally with design, verification, physical design, and manufacturing teams to integrate DFT methodologies early in the design cycle
Drive continuous improvement in test coverage, fault detection, and test time reduction across product families
Select, develop, and evaluate personnel to ensure efficient operation of the DFT function; mentor engineers and foster a culture of technical excellence
Minimum Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, or related field (Master's or PhD preferred)
5+ years of experience in digital design or DFT engineering
Deep expertise in DFT methodologies: scan insertion, ATPG, BIST (Logic/Memory), JTAG, boundary scan, and test compression
Hands-on experience with industry-standard EDA tools (e.g., Synopsys TestMAX, Mentor Tessent)
Strong understanding of SoC/MCU architecture and digital design flows
Proven ability to lead cross-functional teams and deliver results in a fast-paced, high-complexity environment
Excellent communication skills — ability to present technical findings and recommendations to both engineering and executive audiences
Preferred Qualifications
Background in embedded systems or MCU product development
Experience with silicon bring-up, failure analysis, and yield improvement initiatives