We are at a pivotal moment where technology is rapidly evolving, and we have some exciting opportunities within our MCU organization that place us right at the center of this transformation.
Our current work is focused on developing solutions for high-growth markets such as AI-driven data centers and emerging domains like humanoid systems. These areas are shaping the future of computing, automation, and intelligent systems, and offer a unique chance to work on cutting-edge technologies with real-world impact.
If you are passionate about solving complex technical challenges and want to contribute to innovations in these fast-growing segments, I encourage you to come forward and apply. This is an opportunity to be part of a journey that is not only technically rewarding but also strategically significant.
Looking forward to seeing many of you take this step.
Texas Instruments is seeking an experienced and highly skilled DFT Lead Engineer to join our silicon design team. In this role, you will serve as a technical leader responsible for defining and driving DFT architecture, methodology, and execution for TI's next-generation semiconductor devices. You will play a pivotal role in mentoring junior engineers, influencing cross-functional design decisions, and ensuring silicon quality and testability at scale.
This is a high-impact role for someone who thrives at the intersection of design, test, and silicon engineering and is ready to take ownership of end-to-end DFT delivery on low cost MCU platforms.
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Responsibilities
Lead DFT architecture definition for complex SoC designs from concept to tape-out
Drive DFT strategy including scan compression, MBIST, JTAG, and hierarchical test
Represent DFT in cross-functional design reviews and technical forums
Own scan insertion, ATPG, and MBIST implementation for low cost MCU.
Define fault coverage targets and ensure test quality standards are met
Lead resolution of complex ATPG, scan chain, and GLS violations
Influence design architecture decisions to improve testability and reduce test cost
Lead silicon bring-up including ATE correlation and debug
Develop and maintain robust DFT automation flows using Tcl, Perl, and Python
Qualifications
5+ years of hands-on DFT engineering experience in the semiconductor industry
Expert-level knowledge in scan insertion, ATPG, MBIST, fault simulation, and DFT sign-off
Advanced proficiency with Cadence tools — Modus (DFT), Genus (Synthesis), and Xcelium (Simulation)
Strong expertise in Verilog and/or VHDL
Advanced scripting skills in Tcl, Perl, and/or Python for flow automation
Familiarity with low-power DFT methodologies including multi-voltage and clock-gated designs
