What You'll Be Doing
Lead and drive execution of scan insertion and ATPG (Automatic Test Pattern Generation) flows for complex IP designs along with a team of talented DFT engineers.
Work closely with RTL and Verification teams to ensure DFT requirements are integrated early in the design cycle.
Analyze/resolve DFT-related issues using tools such as Spyglass DFT, ensuring robust test coverage and manufacturability.
Guide team/Perform scan STA (Static Timing Analysis) to validate timing closure and optimize testability paths.
Use AI tools/flow for DFT tasks execution to improve the efficiency.
Collaborate with cross-functional teams and central DFT methodology team to define and implement best practices for DFT methodologies and flows.
Contribute to the continuous improvement of automation and design flows to boost efficiency and reduce turnaround time.
The Impact You Will Have
Enhance the testability and reliability of cutting-edge ASIC products, reducing defect rates and improving time-to-market.
Drive innovation in DFT flows, setting new standards for quality and efficiency within the organization.
Collaborate with a global team of experienced engineers, fostering a culture of knowledge sharing and continuous learning.
Enable successful silicon validation and ramp-up, directly contributing to customer satisfaction and business growth.
Represent Synopsys as a technical leader in the industry, influencing best practices and future technology directions.
Contribute to the development of next-generation technologies in AI, automotive, and other high-impact sectors.
What You'll Need
BS/MS in Electrical Engineering or Electronics and Communication Engineering with 8+ years of relevant experience.
Past experience of technically leading a team for DFT execution of IP projects. Experience in effective collaboration and stakeholder management with program management, design/verification and design implementation teams.
Proven experience in DFT methodologies, including scan insertion and ATPG for complex ASIC designs.
Proficiency with industry-standard EDA tools such as Spyglass DFT and scan STA analysis suites.
Demonstrated ability to debug and resolve DFT-related issues across multiple project phases.
Some experience of using AI tools for DFT tasks and other basic tasks (script generation/usage) to automate design and test flows.
Basic understanding of digital logic design, and verification principles is also useful.
Who You Are
Collaborative team player who communicates effectively across functions and cultures.
Proactive problem solver, comfortable with ambiguity and rapid change.
Detail-oriented and highly organized, with a commitment to delivering high-quality results.
Inclusive and open-minded, eager to share knowledge and mentor others.
Self-motivated and driven by curiosity, with a continuous learning mindset.
The Team You'll Be A Part Of
You will join a dynamic and innovative front end IP team which includes design, verification and DFT sub teams within Synopsys' Engineering organization in Bangalore. The DFT team is dedicated to advancing ASIC testability and reliability, working collaboratively with design, verification, and software groups across the globe. Our culture values technical excellence, mentorship, and cross-disciplinary innovation, providing opportunities to work on industry-leading products that power the next wave of intelligent systems.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
