Synopsys
From Synopsys's careers page
Status: listed on the employer's own careers page when we last checked (daily). Confirm on their site before applying.
At Synopsys, you will lead the layout organization responsible for advanced SerDes and high-speed connectivity IP that defines industry standards.
We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You have built your career in custom analog and mixed-signal layout, developing a deep understanding that successful tapeouts depend on decisions made during floorplanning, rigorous verification processes, and proactive risk management. Your expertise extends beyond technical execution to include the strategic thinking required to prevent issues before they reach critical stages in the development cycle.
You have progressed from individual contributor to technical leader, establishing methodologies that ensure consistency and quality across complex projects. When your team encounters challenges with EMIR analysis or LVS verification, you provide the technical guidance necessary to resolve issues while developing their problem-solving capabilities. Your approach to execution is disciplined and data-driven. You have successfully managed multiple tapeouts, balanced competing project demands, and maintained schedule integrity through careful planning and clear communication with stakeholders at all levels. At Synopsys, you will lead the layout organization responsible for advanced SerDes and high-speed connectivity IP that defines industry standards.
Lead and manage a layout engineering team delivering custom analog/mixed-signal IC layout for PCIe Gen7/Gen8, UCIe, SerDes, PLLs, PHYs, and power management IP
Direct layout execution from initial floorplanning through tapeout, including resource planning, schedule management, and risk mitigation across concurrent development programs
Establish and implement advanced layout methodologies, automation frameworks, and AI-assisted design tools to enhance quality and efficiency
Collaborate with analog design, digital implementation, verification, CAD, and product engineering organizations to resolve technical challenges and ensure alignment with project objectives
Define and enforce layout standards for DRC, LVS, EMIR, reliability, ESD, and manufacturing compliance across advanced CMOS process technologies
Build organizational capability through recruiting, mentoring, and developing layout engineers and technical leads
The Impact You Will Have
Your team will deliver the physical implementation for industry-leading high-speed connectivity IP deployed in data center, AI infrastructure, and networking applications globally
The methodologies and quality standards you establish will improve first-pass silicon success rates and reduce development cycle times across multiple product portfolios
Your investment in team development will build technical depth and leadership capability within the organization
Your execution discipline will ensure critical programs meet schedule commitments while maintaining the quality standards required for production silicon
The cross-functional collaboration frameworks you implement will strengthen alignment between design, layout, CAD, and process technology teams across global development sites
Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or equivalent professional experience
10+ years of professional experience in custom analog/mixed-signal IC layout design with demonstrated expertise in advanced CMOS process technologies
3+ years of experience managing and developing layout engineering teams
Proven track record delivering high-speed SerDes, PLLs, PHYs, ADC/DACs, or power management circuits through multiple production tapeouts
Comprehensive knowledge of DRC, LVS, EMIR, reliability, ESD, and design-for-manufacturing requirements
Experience with PCIe, UCIe, or other high-speed interface standards is highly valued
You identify potential design-for-manufacturing issues during technical reviews and communicate the implications and mitigation strategies clearly to design teams and management
You assess when direct technical intervention is required versus when coaching and resource connection will better serve both the immediate need and long-term team development
You maintain sufficient technical engagement with ongoing work to accurately assess project health and risk beyond what is reflected in status reports
You have established team environments where engineers proactively communicate challenges, share lessons learned, and collaborate effectively
You provide data-supported recommendations when project timelines or scope changes introduce technical or schedule risk
The Team You'll Be Part Of
Your recruiter will share more about the team structure and mission during the interview process.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
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