Synopsys
From Synopsys's careers page
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At Synopsys, you will lead a team building embedded memories and memory compilers that ship in real products across advanced process nodes.
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You have spent years in the physical layout trenches of SRAM development, and you know that the difference between a memory that meets PPA targets and one that requires three more spins is usually a layout decision made during floorplanning. You understand how bitcell density, array routing, and peripheral placement affect yield, performance, and power in ways that do not show up in early simulations. You have debugged enough DRC violations, LVS mismatches, and EM/IR failures to recognize patterns before they become blockers.
Managing people energizes you because you want your team to have the support, clarity, and technical direction you wish you had earlier in your career. You know how to balance project timelines with technical quality. You can translate a vague requirement from a memory architect into a concrete layout task, and you can explain a complex parasitic issue to a project lead without losing them in the details.
At Synopsys, you will lead a team building embedded memories and memory compilers that ship in real products across advanced process nodes.
Lead a team of SRAM memory layout engineers through the full development cycle, from initial floorplanning and resource allocation to physical verification signoff and product release
Own layout execution for memory arrays, bitcells, peripheral circuits, power distribution networks, and complete memory instances, ensuring they meet PPA, reliability, and manufacturability targets
Drive resolution of complex physical design challenges including DRC, LVS, ERC, antenna violations, EM/IR analysis, routing congestion, and parasitic extraction issues across advanced FinFET and GAA nodes
Manage project schedules, resource allocation, technical dependencies, and risk mitigation across multiple concurrent memory compiler and embedded memory development efforts
Collaborate directly with circuit design, memory architecture, characterization, CAD tool development, physical verification, process technology, and foundry engineering teams to align layout execution with product requirements
Build and improve layout methodologies, automation scripts, design reuse frameworks, and standardization practices that increase team efficiency and reduce development cycle time
Mentor engineers, establish technical best practices, conduct performance reviews, support hiring and onboarding, and grow the technical capability of the layout organization
The Impact You Will Have
Deliver embedded SRAM memories and memory compiler products that meet aggressive PPA targets and enable customer tapeouts on schedule
Reduce layout development cycle time and improve design quality through methodology improvements, automation, and reuse strategies that scale across multiple projects
Build a high-performing layout team with strong technical depth, clear career growth paths, and the ability to handle increasing complexity at advanced nodes
Resolve critical physical design issues that unblock product releases and prevent costly respins or yield losses
Strengthen cross-functional collaboration between layout, circuit design, and verification teams, reducing miscommunication and rework
Establish layout best practices and design standards that improve consistency, quality, and knowledge transfer across the memory IP organization
Enable Synopsys memory IP customers to achieve their performance, power, area, and time-to-market goals by delivering robust, manufacturable memory solutions
Bachelor's or master's degree in electrical engineering, Electronics, Microelectronics, or a related field
7+ years of hands-on experience in SRAM memory layout development, including work on bitcells, arrays, peripheral circuits, and full memory integration
Deep understanding of SRAM architecture, memory compilers, and how layout decisions affect performance, power, area, yield, and reliability
Strong working knowledge of DRC, LVS, ERC, antenna checks, EM/IR analysis, parasitic extraction, and advanced-node layout constraints
Demonstrated experience leading engineering teams or managing complex technical projects with multiple stakeholders and dependencies
Proficiency with industry-standard custom layout tools and physical verification flows, experience with layout automation and scripting is a plus
Experience with SRAM memory compiler development across multiple process technologies and advanced FinFET or GAA nodes is a plus
You can look at a layout floorplan and immediately spot potential routing bottlenecks, power distribution weaknesses, or density issues that will surface later in verification
When a circuit designer asks for a layout change two days before tapeout, you assess the impact, communicate the tradeoffs clearly, and either make it happen or explain why it cannot without creating risk
You give your team enough context to make good decisions on their own, but you stay close enough to catch problems early before they become schedule or quality issues
You can explain a complex EM/IR violation to a project manager in two sentences without losing the technical accuracy, and you can walk a junior engineer through the same issue with enough detail that they learn how to solve it next time
You manage multiple concurrent projects without losing track of dependencies, critical paths, or resource constraints, and you know when to escalate and when to solve it within the team
You build trust with cross-functional teams by delivering what you commit to, communicating proactively when things change, and showing up prepared to technical discussions
The Team You'll Be Part Of
Your recruiter will share more about the team structure and mission during the interview process.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
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