Define and implement characterization methodologies for standard-cell and mixed-signal models, including the deployment of automated EDA flows.
Collaborate with multi-functional teams, including physical design and system architecture, to define interface requirements and implementation constraints.
Own the physical implementation of complex custom blocks, optimizing for timing, power, signal integrity, and layout-dependent effects.
Analyze silicon results post-bring-up to drive improvements in circuit design, characterization models, and future IP architectures.
Drive technical reviews for schematics, layouts, and methodologies to resolve complex cross-disciplinary issues and mitigate architectural risks.
Develop reusable infrastructure, scripts, and documentation to improve engineering productivity and design quality.
Apply expertise in advanced process nodes, including FinFET and GAA, to push the boundaries of ASIC power-delivery and clocking solutions.
Minimum Qualifications
Bachelor’s degree and 7 years of related experience, or Master’s degree plus 4 years of related experience, or PhD plus 1 year of related experience.
Relevant experience should include ASIC, custom digital, standard-cell, or analog/mixed-signal circuit design and implementation.
Preferred Qualifications
Design & IP Development: Proven expertise in designing and optimizing custom digital circuits (e.g., standard cells, low-power cells) and analog/mixed-signal IP (e.g., regulators, oscillators, sensors) with a strict focus on PPA, reliability, and yield.
Methodology & Analysis: Strong background in circuit-level analysis (SPICE, PVT, Monte Carlo, variation) and standard-cell modeling (Liberty, CCS/ECSM, LVF) using industry-standard EDA tools from Cadence, Synopsys, or Siemens.
Physical & Process Implementation: First-hand experience with advanced nodes (FinFET/GAA) and physical implementation flows, including custom layout, parasitic extraction, DRC/LVS, and reliability analysis (EM/IR).
Silicon Lifecycle & Leadership: Demonstrated ability to lead technical reviews, influence ASIC architecture, and get results through silicon bring-up, failure analysis, and model-to-silicon correlation.
Proficiency in automation and scripting (Python, Tcl, or shell) to enhance engineering productivity.
Why Cisco?
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.
