You'll work directly with core micro-architects and RTL designers, and you'll own verification of specific units (e.g. rename/dispatch, issue queues, load-store unit, MMU/TLB, branch prediction, or the retire/commit path) as well as core-level scenarios.
What You'll Do
Own the verification plan for one or more OOO core units: extract testable features from the micro-architecture spec, define stimulus and coverage requirements, and drive them to closure.
Build and extend UVM testbench infrastructure — agents, drivers/monitors, scoreboards, reference models, functional coverage, and assertions (SVA).
Develop constrained-random test generators and directed tests (C/assembly test programs plus SV stimulus) targeting deep pipeline states: speculative execution and misprediction recovery, replay and livelock scenarios, exception/interrupt injection, memory-ordering and coherence corner cases, and privilege/virtual-memory transitions.
Debug regression failures end to end: triage waveforms, correlate RTL state against instruction-by-instruction co-simulation mismatches (PC, write-data, CSR state), and reduce failures to a minimal reproducer with a clear root-cause writeup for the designer.
Drive coverage closure — code, functional, and assertion coverage — including analyzing holes, adding stimulus or coverage waivers with justification, and reporting progress against tapeout milestones.
Maintain and improve regression health: keep failure signatures triaged and bucketed, reduce noise, and improve turnaround time and debuggability of the test flow.
Contribute to the verification environment and tooling: build/run flows, log parsers, failure-signature classification, and CI integration.
Review micro-architecture and RTL changes for verification impact; participate in spec reviews and file spec ambiguities.
Required Qualifications
BS or MS in Electrical/Computer Engineering, Computer Science, or equivalent.
2+ years of professional pre-silicon functional verification experience (MS with strong relevant internship/project experience considered).
Strong SystemVerilog and UVM: you can write and extend testbench components independently, not just author tests in an existing environment.
Solid computer-architecture fundamentals: pipelining, caches and cache hierarchy, branch prediction, register renaming, out-of-order issue and in-order retirement, memory consistency and coherence basics.
Proficiency with a simulator (VCS, Questa, or Xcelium) and waveform debug (Verdi, Visualizer, or similar) — including independently debugging a failing test from log to waveform to root cause.
Working knowledge of assembly and C at the bare-metal level; comfortable reading disassembly and reasoning about instruction streams.
Scripting for automation and analysis: Python, plus shell/Makefile fluency.
Version control and code review workflow (Git).
Preferred Qualifications
Experience verifying an out-of-order or superscalar core
RISC-V experience: familiarity with the unprivileged and privileged specs, and with extensions such as vector (V), hypervisor (H), or atomics (A).
Experience with ISA co-simulation / lockstep golden-model flows (spike or equivalent) and with debugging scoreboard mismatches.
Random instruction-stream test generators (e.g. Sting, RISCV-DV, force-riscv, or an in-house equivalent) — including constraining and extending a generator, not just running it.
Formal property verification for control-logic blocks (JasperGold or VC Formal).
Exposure to memory-model verification, litmus tests, or a coherence/ordering checker.
Performance verification or performance-counter validation experience.
Emulation/FPGA prototyping, or post-silicon bring-up exposure.
Additional Information
- This position requires a successful background and reference checks and satisfactory proof of your right to work in:
- India
Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.
