The ideal candidate will have strong expertise in Design Verification, low-power verification, waveform debugging, power analysis, and cross-functional execution.
Key Responsibilities
Develop and execute DV power vectors covering workloads, power states, transitions, boot flows, retention, reset, and stress scenarios.
Bring up and maintain simulation, emulation, and power-aware verification environments.
Analyze waveforms, activity dumps, power reports, and execution logs to identify meaningful power-analysis windows.
Extract power windows for: Peak & average power Dynamic voltage drop / IR-drop Thermal analysis Pre-silicon vs. post-silicon correlation
Debug vector failures, power-state sequencing issues, missing activity, waveform mismatches, and unexpected power behavior.
Work closely with DV, Design, Power, Physical Design, Emulation, PTE, and Post-Silicon teams.
Maintain traceability across test cases, configurations, waveforms, extracted windows, and vector collateral.
Required Qualifications
Bachelor’s/Master’s degree in Electrical, Electronics, Computer Engineering, or a related field.
7–15 years of experience in Design Verification, power-aware verification, power-vector development, or power analysis.
Strong understanding of: RTL simulation & waveform analysis SystemVerilog / UVM Low-power design concepts Power states, clock gating, retention & isolation Simulation, emulation, GLS, and/or silicon-validation flows Power estimation & activity analysis
Scripting experience with Python, Perl, Shell, or Tcl.
Hands-on experience with waveform-debug and power-analysis tools.
Ability to identify representative, peak, and corner-case power windows.
Strong debugging, analytical, documentation, and communication skills.
Good to Have
UPF / power-intent verification
CPU, SoC, memory, interconnect, or subsystem-level power knowledge
Dynamic voltage drop, IR-drop, VMIN, or thermal analysis
Emulation platforms and large-scale workload execution
Pre-silicon and post-silicon power correlation
Understanding of frequency-voltage operating points and power-performance trade-offs
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