Rivian
From Rivian's careers page
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As a company, we constantly challenge what’s possible, never simply accepting what has always been done.
About Rivian Rivian is on a mission to keep the world adventurous forever. This goes for the emissions-free Electric Adventure Vehicles we build, and the curious, courageous souls we seek to attract. As a company, we constantly challenge what’s possible, never simply accepting what has always been done. We reframe old problems, seek new solutions and operate comfortably in areas that are unknown. Our backgrounds are diverse, but our team shares a love of the outdoors and a desire to protect it for future generations. Role Summary We are seeking an IC Package Design Engineer to join our ASIC team. In this role, you will lead the physical layout, modeling, and analysis of advanced semiconductor packaging solutions for high-performance integrated circuits (ICs). You will collaborate closely with cross-functional teams, including IC Design, Signal/Power Integrity (SI/PI), PCB Layout, Mechanical, Thermal, and Test Engineering, as well as substrate vendors and OSAT partners to deliver robust, cost-effective packaging from concept through volume production. Responsibilities End-to-End Package Layout: Own physical layout execution, including die placement, bump assignment, floor planning, ball map optimization, bump-to-ball fan-out planning, stack-up definition, and layer planning. Advanced Packaging Implementations: Design and develop advanced IC packaging solutions, including flip-chip BGA (FCBGA), System-in-Package (SiP), and 2.5D/3D IC architectures (e.g., interposers, CoWoS, EMIB, FOWLP). Silicon, Package & Board Co-Design: Partner closely with silicon and system teams to align on die/package/PCB co-design, floor planning, ball map, and interposer routing. High-Speed & Power Delivery Network: define and route high speed interfaces (e.g., DDR, PCIe, SerDes), design robust Power Delivery Networks (PDN) with high di/dt requirement EDA Tooling: Create, manage, and validate complex package layouts using industry-standard EDA tools (e.g., Cadence APD/SiP, Cadence Virtuoso, Synopsys 3DICC, Siemens Xpedition). Verification & Signoff: Run Design Rule Checking (DRC), Layout vs. Schematic (LVS) checks, netlist verification, and strict Design for Manufacturing (DFM/DFT) reviews. Manufacturing Collateral: Generate and validate complete manufacturing collateral (Gerbers, ODB++, BOMs) for tapeout and manufacturing release. Multi-Disciplinary Convergence: Work directly with SI/PI, thermal, and mechanical engineering teams to achieve design convergence across power, signal integrity, thermal, and mechanical reliability constraints. Vendor & OSAT Integration: Interface with foundries, substrate vendors, and OSAT partners to evaluate design feasibility, select packaging materials and design rules, maximize manufacturing yield, and execute smooth tapeouts. Bring-up & Test Support: Assist in lab bring-up, debugging, and silicon validation for packaged devices; collaborate with test engineering teams on probe card and test socket interface design. Workflow Automation: Develop and implement scripting tools (e.g., Python, Tcl, Perl, MATLAB) to automate layout flows and enhance design efficiency. AI/ML Innovation: Explore and drive adoption of AI/ML-enabled methodologies (e.g., predictive analytics, layout optimization, automated rule checks) to scale productivity and decision-making. Qualifications Education: B.S. or M.S. in Electrical Engineering, Computer Engineering, Materials Science, Mechanical Engineering, or a related field. Experience: 3+ years (5+ years preferred) of hands-on experience in semiconductor package and substrate layout design, particularly for high-speed (SerDes) and high di/dt IC applications. EDA Tools Proficiency: Proven expertise with industry-standard packaging EDA tools such as Cadence Allegro APD/SiP, Cadence Virtuoso, Synopsys 3DICC, Siemens Xpedition Package Designer, or Calibre/KLayout. Technical Fundamentals: Strong foundational knowledge of electromagnetics, impedance control, crosstalk minimization, substrate materials, thermal management, and mechanical reliability. Manufacturing Standards: Solid understanding of DFM/DFT principles, JEDEC standards, DRC/LVS signoff flows, and reliability qualification processes. Advanced Packaging Experience: Hands-on experience with heterogeneous integration, chiplet architectures, silicon interposers, and 2.5D/3D IC packaging technologies is preferred. Ecosystem & Vendor Track Record: A strong track record of working directly with top-tier OSATs, substrate manufacturers, and foundry packaging teams is preferred. Automation & Scripting: Experience writing scripts (Python, Tcl, Perl, MATLAB) for workflow automation or leveraging modern AI/ML applications within engineering workflows is preferred. Pay Disclosure The salary range for this role is $171,000 - $272,000 for Irvine, CA based applicants and is $186,000 - $296,000 for Palo Alto, CA based applicants. This is the lowest to highest salary we in good faith believe we would pay for this role at the time of this posting. An employee’s position within the salary range will be based on several factors including, but not limited to, specific competencies, relevant education, qualifications, certifications, experience, skills, geographic location, shift, and organizational needs. The successful candidate may be eligible for annual performance bonus and equity awards. We offer a comprehensive package of benefits for full-time and part-time employees, their spouse or domestic partner, and children up to age 26, including but not limited to paid vacation, paid sick leave, and a competitive portfolio of insurance benefits including life, medical, dental, vision, short-term disability insurance, and long-term disability insurance to eligible employees. You may also have the opportunity to participate in Rivian’s 401(k) Plan and Employee Stock Purchase Program if you meet certain eligibility requirements. Full-time employee coverage is effective on their first day of employment. Part-time employee coverage is effective the first of the month following 90 days of employment. More information about benefits is available at rivianbenefits.com. Equal Opportunity Rivian is an equal opportunity employer and complies with all applicable federal, state, and local fair employment practices laws. All qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, ancestry, sex, sexual orientation, gender, gender expression, gender identity, genetic information or characteristics, physical or mental disability, marital/domestic partner status, age, military/veteran status, medical condition, or any other characteristic protected by law. Rivian is committed to ensuring that our hiring process is accessible for persons with disabilities. If you have a disability or limitation, such as those covered by the Americans with Disabilities Act, that requires accommodations to assist you in the search and application process, please email us at candidateaccommodations@rivian.com. Candidate Data Privacy and Technology Rivian may collect, use and disclose your personal information or personal data (within the meaning of the applicable data protection laws) when you apply for employment and/or participate in our recruitment processes (“Candidate Personal Data”). This data includes contact, demographic, communications, educational, professional, employment, social media/website, network/device, recruiting system usage/interaction, security and preference information. Rivian may use your Candidate Personal Data for the purposes of (i) tracking interactions with our recruiting system; (ii) carrying out, analyzing and improving our application and recruitment process, including assessing you and your application and conducting employment, background and reference checks; (iii) establishing an employment relationship or entering into an employment contract with you; (iv) complying with our legal, regulatory and corporate governance obligations; (v) recordkeeping; (vi) ensuring network and information security and preventing fraud; and (vii) as otherwise required or permitted by applicable law. Rivian may share your Candidate Personal Data with (i) internal personnel who have a need to know such information in order to perform their duties, including individuals on our People Team, Finance, Legal, and the team(s) with the position(s) for which you are applying; (ii) Rivian affiliates; and (iii) Rivian’s service providers, including providers of background checks, staffing services, and cloud services. Rivian may transfer or store internationally your Candidate Personal Data, including to or in the United States, Canada, the United Kingdom, and the European Union and in the cloud, and this data may be subject to the laws and accessible to the courts, law enforcement and national security authorities of such jurisdictions. How We Use AI in Our Hiring Process: To ensure transparency, we want candidates to know that Rivian uses iCIMS Talent Cloud Artificial Intelligence (TCAI) and AI-enabled tools to assist with screening, reviewing, organizing and highlighting profiles and applications that match the key requirements for each role. AI does not make hiring decisions: Qualified candidate applications are reviewed by a member of our team, and all decisions throughout the process are made by humans. We use AI to support efficiency and consistency, not to replace human judgment. We are committed to a fair, thoughtful, and equitable experience for every candidate. Participation in AI profile matching is entirely voluntary. If you prefer that your profile not be used in this process, you can opt out at any time. Opting out means your profile will be excluded from automated matching and will not be surfaced for additional roles through this system. Your current application remains active and will not be affected in any way. Interview Integrity & AI Policy Our interview process is designed to evaluate your personal technical foundation, real-time problem-solving logic, and structured capabilities. Therefore, the use of assistive generative AI tools to formulate or deliver your solutions during live interview sessions is not permitted. We care most about how you think — how you make sense of unclear requirements, weigh trade-offs, and explain why you chose one approach over another. We value your unique human perspective, your authenticity, and the journey it takes to reach a solution. Please note that we are currently not accepting applications from third party application services. End-to-End Package Layout: Own physical layout execution, including die placement, bump assignment, floor planning, ball map optimization, bump-to-ball fan-out planning, stack-up definition, and layer planning. Advanced Packaging Implementations: Design and develop advanced IC packaging solutions, including flip-chip BGA (FCBGA), System-in-Package (SiP), and 2.5D/3D IC architectures (e.g., interposers, CoWoS, EMIB, FOWLP). Silicon, Package & Board Co-Design: Partner closely with silicon and system teams to align on die/package/PCB co-design, floor planning, ball map, and interposer routing. High-Speed & Power Delivery Network: define and route high speed interfaces (e.g., DDR, PCIe, SerDes), design robust Power Delivery Networks (PDN) with high di/dt requirement EDA Tooling: Create, manage, and validate complex package layouts using industry-standard EDA tools (e.g., Cadence APD/SiP, Cadence Virtuoso, Synopsys 3DICC, Siemens Xpedition). Verification & Signoff: Run Design Rule Checking (DRC), Layout vs. Schematic (LVS) checks, netlist verification, and strict Design for Manufacturing (DFM/DFT) reviews. Manufacturing Collateral: Generate and validate complete manufacturing collateral (Gerbers, ODB++, BOMs) for tapeout and manufacturing release. Multi-Disciplinary Convergence: Work directly with SI/PI, thermal, and mechanical engineering teams to achieve design convergence across power, signal integrity, thermal, and mechanical reliability constraints. Vendor & OSAT Integration: Interface with foundries, substrate vendors, and OSAT partners to evaluate design feasibility, select packaging materials and design rules, maximize manufacturing yield, and execute smooth tapeouts. Bring-up & Test Support: Assist in lab bring-up, debugging, and silicon validation for packaged devices; collaborate with test engineering teams on probe card and test socket interface design. Workflow Automation: Develop and implement scripting tools (e.g., Python, Tcl, Perl, MATLAB) to automate layout flows and enhance design efficiency. AI/ML Innovation: Explore and drive adoption of AI/ML-enabled methodologies (e.g., predictive analytics, layout optimization, automated rule checks) to scale productivity and decision-making. Education: B.S. or M.S. in Electrical Engineering, Computer Engineering, Materials Science, Mechanical Engineering, or a related field. Experience: 3+ years (5+ years preferred) of hands-on experience in semiconductor package and substrate layout design, particularly for high-speed (SerDes) and high di/dt IC applications. EDA Tools Proficiency: Proven expertise with industry-standard packaging EDA tools such as Cadence Allegro APD/SiP, Cadence Virtuoso, Synopsys 3DICC, Siemens Xpedition Package Designer, or Calibre/KLayout. Technical Fundamentals: Strong foundational knowledge of electromagnetics, impedance control, crosstalk minimization, substrate materials, thermal management, and mechanical reliability. Manufacturing Standards: Solid understanding of DFM/DFT principles, JEDEC standards, DRC/LVS signoff flows, and reliability qualification processes. Advanced Packaging Experience: Hands-on experience with heterogeneous integration, chiplet architectures, silicon interposers, and 2.5D/3D IC packaging technologies is preferred. Ecosystem & Vendor Track Record: A strong track record of working directly with top-tier OSATs, substrate manufacturers, and foundry packaging teams is preferred. Automation & Scripting: Experience writing scripts (Python, Tcl, Perl, MATLAB) for workflow automation or leveraging modern AI/ML applications within engineering workflows is preferred.
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