Key Responsibilities
Validation Strategy & Planning
Define and drive system-level validation strategy for complex SoC programs.
Develop comprehensive validation plans spanning pre-silicon and post-silicon phases.
Identify high-risk customer use cases and translate them into executable validation content.
Define stress, power, performance, scalability, and corner-case validation scenarios.
Establish platform coverage plans across Veloce, RUMI, FPGA, and Silicon environments.
Drive coverage closure based on previous program learnings and emerging architectural risks.
Content Leadership
Own end-to-end content strategy, roadmap, execution, readiness reviews, and delivery milestones.
Drive content architecture and test plan reviews across multiple subsystem domains.
Ensure content quality, scalability, reusability, and maintainability.
Lead content stabilization, qualification, and regression activities.
Drive system-level content releases for HVV, SLT, and production screening environments.
Technical Leadership
Partner with Architecture, Design, DV, Firmware, and Software teams to define validation requirements.
Lead debug of complex silicon, emulation, firmware, and software issues.
Drive root-cause analysis and corrective action plans for critical product issues.
Influence future validation methodologies, frameworks, and automation roadmaps.
Champion innovative approaches leveraging AI/GenAI-driven validation methodologies.
Program Execution
Drive cross-functional execution across multiple global sites.
Coordinate content scrums, program reviews, readiness assessments, and milestone tracking.
Manage external dependencies and risk mitigation plans.
Partner with Emulation, System Debug, and Execution teams to drive program success.
Provide regular executive-level status updates and technical reviews.
People & Organizational Leadership
Mentor senior engineers and future technical leaders.
Build high-performing global content teams.
Drive engineering excellence, execution rigor, and scalable operating models.
Influence resourcing, organizational planning, and capability development efforts.
Required Qualifications
Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
8+ years of experience in SoC validation, bring-up, architecture validation, firmware, or system software.
Strong understanding of modern SoC architectures including
CPUs (ARM architectures)
Memory subsystems (DDR/HBM/LLCC)
Interconnects and NoC
Power management systems
Security and virtualization architectures
Peripheral subsystems
Proven experience with pre-silicon and post-silicon validation.
Strong debugging and root-cause analysis skills.
Demonstrated technical leadership across geographically distributed teams.
Excellent communication and stakeholder-management skills.
Preferred Qualifications
Experience leading validation for flagship mobile, compute, AI, automotive, or server-class SoCs.
Expertise in system-level content development and validation frameworks.
Experience with emulation environments.
Knowledge of performance, power, reliability, and production-screening methodologies.
Experience leveraging automation, analytics, and AI-based engineering productivity solutions.
Track record of driving large cross-functional programs from concept to production.
Why Join Us?
This role provides the opportunity to shape validation strategy for industry-leading Snapdragon platforms while influencing architecture, methodology, AI-driven validation workflows, and next-generation silicon products across multiple business units. You'll work with some of the industry's most accomplished architects and engineers to solve the toughest system-level challenges at scale.
Minimum Qualifications
- Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
- OR
- Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
- OR
- PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
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Pay range and Other Compensation & Benefits
$174,400.00 - $261,600.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.
