Role and Responsibilities
Provide technical and organizational leadership for the CHS Datacenter package design team; recruit, develop, mentor, and retain a high-performing team of package architects, physical designers, and technical leads.
Own the end-to-end advanced package architecture and design strategy for Datacenter and high-performance compute (HPC) products, from early feasibility and technology selection through design release, qualification, production ramp, and sustaining support.
Drive architecture selection and configuration optimization for advanced multi-die packages, including 2.5D/3D integration, HBM, silicon interposers, silicon bridges, high-density organic substrates, and other emerging chiplet integration technologies.
Lead chip-package-board co-design across silicon floorplan, die partitioning, bump maps, HBM and chiplet placement, package pinout, routing architecture, power delivery, package size, board escape, and system constraints.
Partner with silicon design, physical design, platform architecture, SI/PI, thermal, mechanical, product engineering, manufacturing, and supply-chain teams to balance performance, power, thermal, reliability, yield, schedule, and cost objectives.
Guide Package/SiP physical design, layout optimization, design verification, tapeout, design reviews, and release readiness; establish clear ownership, technical checkpoints, and execution plans across the team.
Define package-level electrical requirements for high-speed and high-bandwidth interfaces, including HBM, UCIe and other die-to-die links, PCIe, DDR, and high-speed SerDes; ensure package designs meet signal-integrity and power-integrity targets.
Drive thermal-mechanical co-design and reliability risk mitigation for high-power, large-body packages, including warpage, stress, assembly interactions, cooling interfaces, and package-board interactions.
Establish and continuously improve scalable package design methodology, CAD infrastructure, automation, DRC/DFM/ERC signoff, data management, design reviews, and release processes.
Lead technical engagement with foundries, OSATs, substrate suppliers, EDA vendors, and technology partners to define design rules, evaluate new capabilities, resolve technical issues, qualify technologies, and support production ramp and yield improvement.
Develop package technology and capability roadmaps aligned with Qualcomm Datacenter product plans; identify technology gaps, assess technical and supply risks, and drive mitigation plans and executive-level recommendations.
Create a culture of technical excellence, collaboration, accountability, and innovation; coach senior engineers, develop successors and technical leads, and raise package-design capability across the broader organization.
Represent package engineering in program and executive reviews, clearly communicating architecture tradeoffs, technical risks, resource needs, dependencies, and closure plans.
Skills
The Principal Engineer / Director brings technical depth, leadership experience, and has demonstrated capability in the following areas:
Proven leadership of advanced package design or package architecture teams, including hiring, mentoring, performance development, workload planning, and building technical leadership capacity.
Deep expertise in advanced semiconductor packaging for AI, HPC, server, or networking products, including multi-chiplet 2.5D/3D integration, HBM, silicon interposers, silicon bridges, Flip-Chip BGA, and high-density substrates.
Strong system-level understanding of chip-package-board interactions and the ability to translate product performance, power, thermal, reliability, cost, and schedule goals into executable package requirements.
Expert knowledge of package architecture and physical design, including die and HBM placement, bump planning, package pinout, routing topology, layer-stack optimization, power/ground planning, board escape, and manufacturability.
Strong competency in package SI/PI and electromagnetic design for high-speed I/O and power delivery, including transmission-line behavior, crosstalk, return paths, S-parameters, RLGC models, PDN impedance, and decoupling strategy.
Working knowledge of package thermal-mechanical design and reliability considerations, including warpage, stress, material interactions, assembly process risks, thermal interfaces, failure mechanisms, and qualification requirements.
Expertise with Cadence APD/SiP and/or Siemens Xpedition Package Designer, including Constraint Manager, design-rule definition, in-line checking, DRC, DFM, ERC, and package release flows.
Ability to interpret and guide analyses using package extraction and SI/PI tools such as XtractIM, PowerSI, HFSS, Q3D, or equivalent industry tools.
Demonstrated ability to define and deploy design methodologies, automation, verification strategies, review checklists, metrics, and continuous-improvement initiatives across a design organization.
Excellent executive communication, cross-functional influence, technical decision-making, and conflict-resolution skills, with the ability to communicate complex tradeoffs to engineering and business leadership.
Strong partnership skills with foundries, OSATs, substrate suppliers, EDA vendors, and internal product organizations, including experience driving issue resolution across organizational boundaries.
Preferred Qualifications
Master's degree or Ph.D. in Electrical Engineering, Mechanical Engineering, Materials Science, Chemical Engineering, or a related field, with 15+ years of relevant semiconductor and packaging experience; equivalent industry experience may be considered.
Demonstrated record of leading and developing an advanced package engineering organization or a substantial technical team supporting multiple complex products.
Experience owning 2.5D/3D multi-die package architecture and execution for high-power AI, HPC, server, accelerator, or networking products from concept through production.
Direct experience integrating compute SoCs or chiplets with HBM and delivering silicon-interposer, silicon-bridge, or equivalent high-density package solutions.
Experience defining package technology roadmaps and influencing silicon floorplan, bump architecture, die-to-die topology, substrate/interposer architecture, board interfaces, thermal solution, and product cost.
Proven understanding of HBM, UCIe or other die-to-die interfaces, PCIe, DDR, and high-speed SerDes, including their package-level SI/PI and layout implications.
Experience with advanced substrate manufacturing, materials, stackups, design rules, assembly processes, package qualification, yield learning, and typical package failure mechanisms.
Experience working directly with leading foundries, OSATs, substrate suppliers, and EDA partners to evaluate, develop, qualify, and ramp new package technologies.
Experience with Calibre or equivalent physical-verification tools and with establishing package signoff criteria for DRC, DFM, ERC, SI/PI, thermal-mechanical, and release reviews.
Demonstrated innovation through package architecture, methodology, automation, patents, publications, or industry-standard engagement is highly desirable.
Proven ability to operate effectively in a matrixed global organization and to lead through influence across silicon, package, board, system, manufacturing, and supplier teams.
Minimum Qualifications
- Bachelor's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 8+ years of System/Package Design/Technology Engineering or related work experience.
- OR
- Master's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 7+ years of System/Package Design/Technology Engineering or related work experience.
- OR
- PhD in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 6+ year of System/Package Design/Technology Engineering or related work experience.
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Pay range and Other Compensation & Benefits
$210,000.00 - $315,000.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.
