ATPG using standard industry tools to ensure high-quality test patterns (Stuck-At, At-Speed, Path-Delay etc) for maximum test coverage, utilize scan compression & scan data streaming techniques to reduce test time.
Design & implement MBIST & LBIST architecture in RTL.
Collaborate with Physical design teams to resolve DFT related timing violations.
Gate Level Timing & Power Aware simulations.
Silicon Bring-Up
Partner with Test Engineers to bringup initial Silicon.
Diagnose and resolve failing patterns & drive yield improvements.
Automation: Write and maintain scripts (Python, Tcl, or Perl) to automate the DFT insertion and verification flows
What You'll Need
AI Skills: Experience deploying agentic AI tools for optimizing semiconductor workflows.
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Pay range and Other Compensation & Benefits
$100,800.00 - $150,800.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer.
