Key Responsibilities
1. Test Process Development & Optimization
Develop, qualify, and release test processes for new products (NPI to Production transition).
Define test methodologies, limits, and guard bands based on characterization data.
Optimize test programs to improve throughput, test time, and cost efficiency.
2. Yield Monitoring & Improvement
Monitor daily test yield performance and identify yield loss drivers.
Perform Pareto analysis on failures.
Drive root cause analysis (RCA) and implement corrective/preventive actions (CAPA).
Collaborate with cross-functional teams (Assembly, Design, Wafer Fab) to resolve systemic issues.
3. Defect Analysis & Troubleshooting
Investigate abnormal test trends (e.g., IDSS shifts, leakage, parametric drift).
Perform correlation studies between wafer sort, final test, and reliability data.
Support failure analysis (FA) and validate containment actions.
4. Test Program & Equipment Support
Support test program development and debug on ATE platforms (e.g., Advantest, Teradyne).
Ensure proper handler/prober interface and test setup optimization.
Work with equipment engineering to resolve tester hardware issues.
5. Process Control & SPC
Implement and maintain SPC controls (UCL/LCL, Cpk, Ppk) for critical parameters.
Track key metrics such as yield, test escapes, retest rate, and DPPM.
Establish control plans and reaction plans for out-of-control conditions.
6. Continuous Improvement & Cost Reduction
Drive test cost reduction initiatives (test time, multisite optimization, program efficiency).
Improve productivity through automation and standardization.
Lead yield step-up plans following excursions or recovery events.
7. Documentation & Reporting
Prepare technical reports, yield summaries, and management updates.
Document test procedures, specifications, and engineering change notices (ECNs).
Ensure compliance with quality standards (ISO, customer requirements).
Key Performance Indicators (KPIs)
Test yield vs target (%)
Test time reduction (%)
DPPM / test escape rate
Retest rate / on-hold rate
SPC stability (Cpk, UCL compliance)
Cycle time impact (test-related)
Requirements
Education
Bachelor’s or Master’s degree in
Electrical Engineering
Electronics Engineering
Semiconductor Engineering or related field
Experience
2–5+ years in semiconductor test/process engineering (or fresh graduates with strong internship exposure).
Experience in Assembly & Test (back-end) environment preferred.
