We are looking for a Senior Package Design Engineer to join the team.
#SCHIE #CSME #SMPE
Responsibilities
The Senior Package Design Engineer will be responsible for providing expertise, insight, and support to the Silicon development team through the entire life cycle of the product. In this role, you will be responsible for the design and implementation of new custom Silicon devices, in particular substrate, interposer, and bridge design. In addition, you will work with product architects, package technologists, and systems platform team on co-design and optimization of the silicon devices, through the whole product life cycle.
Specific responsibilities to include
Own 2.5D/3D package designs (substrate, interposer and bridge) for Azure datacenter silicon from definition to tapeout.
Develop package architecture and floorplans for chiplet-based designs using advanced packaging technologies such as CoWoS and HBM integration.
Drive package and PCB co-design: define BGA ballout and bump plans and optimize floorplans with SI/PI, silicon PD/RTL, PCB, DFT and ATE teams to meet system-level specs.
Do package layout and routing in industry-standard EDA tools (e.g., Cadence APD/Allegro), and develop scripts and automation to improve design efficiency.
Run package design signoff (DRC, LVS, LEC and DFM) and drive closure of all issues before tapeout.
Define and maintain package design requirements and specs, and keep design data, versions and documentation complete and traceable.
Work with silicon and platform architects, board designers, and thermal, power and performance engineers to balance trade-offs and close on design decisions.
Work with package technologists on the evaluation and recommendation of new packaging technology, device/package qualification and supplier assessment
Work with external partners (OSATs, substrate and interposer suppliers, design-service partners) on design rules, design reviews and tapeout deliverables.
Help design test vehicles that validate new package technologies and design rules.
Identify design risks in new technologies and tool flows early, propose mitigations, and report status and issues to program leadership.
Manage die-to-interposer-to-substrate connectivity and netlists across multi-die designs, and keep them in sync through design changes (ECOs).
Design the package power delivery network (planes, layer stack-up, decoupling capacitor placement) with PI engineers to meet power integrity targets.
Generate and deliver package design data and extracted models to SI/PI, thermal and board teams for system-level analysis, and drive design iterations from the results.
Evaluate and improve package design flows and methods, review designs, and mentor engineers.
Qualifications
Required Qualifications
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.
Other Requirements
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.
Preferred Qualifications
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.
Master’s Degree in Engineering or Hard Science areas related to Semiconductor Packaging
Specific experience with Advanced Semiconductor Package technologies (e.g. BGA/2.5D/3D)
Master’s Degree with 15 years of experience in semiconductor package product development
10+ years hands-on experience in Semiconductor Package design, development, manufacturing, supplier management or quality management
Specific experience with Advanced Semiconductor Package technologies (e.g. BGA/2.5D/3D)
Foundation in advanced packaging technologies, manufacturing and supplier management
Proficient in IC package or PCB board layout CAD tools Cadence Allegro*
Working knowledge in high-speed signaling, layout, electrical, mechanical and thermal co-designs.
Working knowledge in 2D and 3D simulation tools for full package layout extractions for power and signals analysis
Experience with OSAT, Supplier & Foundry technologies.
Experience in physical failure analysis
Experience in subcontract supplier management.
Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.
- Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
- https://careers.microsoft.com/us/en/us-corporate-pay
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.
