Debug and identify root causes of failures using data analysis, electrical characterization, and physical analysis techniques, adjusting testing strategies accordingly.
Optimize test flows and pattern sets to improve test time, throughput, and overall efficiency.
Support testing of new architectures, process nodes, and device functionality.
Minimum Qualifications
Experience in digital circuits, including understanding defect mechanisms and potential failure modes.
Background in designing test methods and developing program test patterns for digital logic circuits.
Proficiency in debugging test patterns and test scripts across various software and hardware environments.
Programming skills in Python, Java, Unix, Perl, Shell, or C++.
Strong algorithmic problem-solving approach.
Working knowledge of Verilog navigation and simulation.
Preferred Qualifications
Understanding of computer architecture, system‑level behavior, and memory subsystem interactions.
Knowledge of device physics principles related to DRAM technology.
Experience with burn‑in characterization and related methodologies.
Demonstrated ability to drive yield improvement initiatives and test strategy enhancements.
Proven track record of implementing new DFT methods to improve testing efficiency and coverage.
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