Learning the Power Management, Memory and SoC debug architecture and microarchitecture by debugging failures to the root cause
Developing and utilizing various debug and validation tools and/or methodologies to implement validation plans with the goal being to ensure a solid design
Participating in the debug of failures on silicon and developing new testing strategies to detect these failures on RTL models
Developing debugging tools and software
Qualifications
Minimum Qualifications
Candidate must have either a BS or MS in Computer Science, Computer Engineering or Electrical Engineering.
Extensive Pre-silicon and Post-silicon Track record of driving debug tools enabling and validation, improvements and getting them adopted by others
Proven record of working across validation teams to solve problems
Expert of HW and SW Interaction and debug to root cause
Experience working across validation, architecture, SW, design teams and Post-Si to resolve debug issues
Minimum 4 yrs experience with DFD/DFT
Minimum 8 yrs experience with writing validation plans and software to implement those validation plans
Minimum 4 yrs experience with Programming languages/Scripting: C, Python, Verilog and System Verilog
Minimum 4 yrs experience with computer architecture
Preferred Qualifications
4yrs+ experience with Design for Debug/Design for Test
4yrs+ experience with validation or testing experience
3yrs+ experience with industry standards such as ATB, Core sight, JTAG
Experience with Tessent tool would be a plus
2+ experience in Emulation and Post-Si support
Job Type
Experienced Hire
Shift
Shift 1 (India)
Primary Location
India, Bangalore
Additional Locations
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
- Work Model for this Role
- This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
