Test Infrastructure / Automation: Design, execute, and continuously optimize validation procedures, specialized test automation frameworks, and system margin analysis tooling.
Post-Silicon Debug / Design Collaboration
Complex Failure Triage: Drive deep-dive debug for electrical design features, identifying root causes for functional, parametric, and triage failures.
Lead DOEs: Formulate and execute multi-variable Design of Experiments (DOEs) in close collaboration with circuit design, logic, and pre-silicon teams to drive silicon issues to resolution.
I/O Interaction Testing: Characterize complex interactions between electrical design elements, board-level environments, and silicon features using post-silicon validation infrastructure.
Firmware Optimization/Cross-Functional Alignment
MRC Analysis / Tuning: Analyze, refine, and optimize Memory Reference Code (MRC) steps, calibration values, and firmware algorithms for margin, power, and quality improvements.
Cross-Team Integration: Collaborate directly with architecture, circuit design, pre-silicon verification, and system integration teams to ensure robust validation coverage across the entire memory subsystem.
Technical Guidance: Provide technical direction and mentorship to junior validation engineers on validation methodologies and debug techniques.
Qualifications
Minimum Qualifications
Education / Experience
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 6+ years of industry experience, OR
Master's degree with 4+ years of industry experience, OR
PhD with 2+ years of industry experience.
Core Technical Experience (Must meet all)
4+ years of hands-on experience in memory electrical validation, including Signal Integrity Validation (SIV) and Signal Margin Validation (SMV).
4+ years of experience in analog/mixed-signal circuit fundamentals, electrical calibration methodologies, and post-silicon memory validation/debug processes.
Solid functional knowledge of Memory Reference Code (MRC) firmware execution paths, parameters, and debug flows for root-cause analysis.
Preferred Qualifications
6+ years of experience in high-speed mixed-signal IP electrical validation, high-speed I/O characterization, or signal integrity (SI/PI) analysis.
Deep domain experience with modern high-speed memory technologies (e.g., DDR5, LPDDR5/5X, LPDDR6) and JEDEC interface specifications.
Proven track record of leading complex root-cause debug investigations (DOEs) across multidisciplinary teams (Design, Logic, FW).
Proficiency with high-speed lab equipment (oscilloscopes, BERTs, logic analyzers) and scripting languages (Python, C/C++) for test automation and data analysis.
Job Type
Experienced Hire
Shift
Shift 1 (Malaysia)
Primary Location
Malaysia, Penang
Additional Locations
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
- Work Model for this Role
- This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
