Memory pathfinding activities and power, performance and area (PPA) optimization through design technology co-optimization (DTCO) and product design enablement.
Memory bit-cell and complex periphery IC layout and automation.
Memory array/IP design, memory circuit innovation, test-chip design.
Pre-Si verification, post-Si validation and debugging to enable yield and parametric tracking/ramp.
Qualifications
You must possess the minimum qualifications listed below to interview for this position. Preferred qualifications are not required but may work to your advantage during the interview process.
Minimum Qualifications
Master degree in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related discipline, including 4+ years of professional experience gained through either internships or full-time employment Or a PhD in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related discipline.
Technical Experience
Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM.
Design trade-offs between power, performance, and area (PPA).
Custom digital circuit design, simulation, layout design, and verification.
Knowledge of EDA tools used for custom digital and memory circuit design.
Preferred Qualifications
PhD with 1-2 years of professional experience gained through either internships or full-time employment.
Design technology co-optimization (DTCO).
Post-Si validation experience.
Knowledge of the CMOS ASIC design flow.
Job Type
Experienced Hire
Shift
Shift 1 (United States of America)
Primary Location
US, Oregon, Hillsboro
Additional Locations
US, Arizona, Phoenix, US, California, Santa Clara, US, Texas, Austin
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
- Work Model for this Role
- This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
