Key Responsibilities
Develop logic designs, register transfer level (RTL) coding, and simulations required for IP blocks, functional units, and subsystems.
Define architecture and microarchitecture features for the IP block being designed.
Apply strategies, tools, and methods to optimize RTL design for power, performance, area, and timing targets.
Strong knowledge of AXI, AXI-Lite, APB, parity/ECC schemes, and transaction error handling.
Experience with secure MMIO, access-control/firewall logic, or privilege-based filtering.
Experience with RAS concepts such as fault containment, poison, interrupt generation, logging, and recovery-oriented design.
Support SoC customers with seamless integration and verification of IP blocks.
Telemetry and debug are both observability functions rather than primary Datapath functions.
Drive compliance with quality assurance standards to enable smooth IP handoff within the SoC development process.
Qualifications
Minimum Qualifications
Bachelor's degree in electrical engineering, Computer Engineering, or related field.
A minimum of 8 years of experience in logic design and RTL development.
Proficiency in hardware description languages such as Verilog, System Verilog.
Strong understanding of digital design principles, including timing analysis, power optimization, and area trade-offs.
Experience with industry-standard EDA tools for design and simulation (e.g., Synopsys, Cadence, Mentor Graphics).
Knowledge of IP block integration workflows within SoC designs.
Expertise in RAS/debug/security/telemetry.
Preferred Qualifications
Master's or PhD degree in Electrical Engineering, Computer Engineering, or related field.
10+ years of professional experience encompassing complex IP logic design for high-performance applications.
Demonstrated expertise in architecture and microarchitecture definition.
Familiarity with advanced verification methodologies such as UVM or formal verification techniques.
Strong communication and collaboration skills, with a proven ability to work effectively in cross-functional teams.
A mindset for continuous learning and improvement, with an eagerness to tackle challenging, innovative design projects.
Take the next step in your career and become part of Intel's world-class engineering team, shaping the future of technology with groundbreaking innovations. Apply today to make an impact.
Job Type
Experienced Hire
Shift
Shift 1 (India)
Primary Location
India, Bangalore
Additional Locations
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
- Work Model for this Role
- This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
