You will work with IP and integration design teams to understand the design and functional-mode behaviors of the logic and circuits. You will micro-architect DFT features which are compatible with the specific product/post-silicon requirements and constraints. You will assist in the RTL and schematic implementation and pre-silicon validation and debug of these DFT features. You will also be expected to deliver high-quality documentation for consumption by the post-silicon teams who will use the DFT features.
Qualifications
Component Design Engineers are responsible for the design and development of electronic components. Responsibilities may include: the design of chip layout circuit design, circuit checking, device evaluation and characterization, documentation of specifications, prototype construction and checkout, modification and evaluation of semiconductor devices and components, performing developmental and/or test work, reviewing product requirements and logic diagrams, planning and organizing design projects or phases of design projects. Responds to customer/client requests or events as they occur. Develops solutions to problems utilizing formal education and judgement
JD for Physical Design
No Of positions:- 18
Independent planning and execution of Netlist-to-GDSII.
Full exposure to all aspects of design flows like floor planning, placement, CTS, routing, crosstalk avoidance, physical verification.
Should have good exposure to high frequency design convergence and exposure to physical design methodology.
3+ years of experience in IC design Experience in leading block level or chip level Timing closure & Physical Design activities. Work independently in the areas of RTL to GDSII implementation.
Ability to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc.
Knowledge of low power flow (power gating, multi-VT flow, power supply management etc.).
Circuit level comprehension of time critical paths in the design. Tcl/Perl scripting.
Willing to handle technical deliveries with a small team of engineers.
Well versed with the level timing closure (STA), timing closure methodologies, ECO generation and predictable convergence.
Well versed with parasitic extraction, LVS/DRC and other Physical verification checks.
Should be able to provide clear directions to the team wrt PNR issues.
Drive methodology with help of local and external CAD/EDA teams for faster design convergence.
Well aware of place and route methodologies and hands on experience with timing convergence.
Qualification: Strong problem-solving skills and teamwork, Self-motivated, excellent verbal and written communication. Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.)
Urgent Openings for RTL Verification /Analog Layout/Physical Design Engineer with our Esteemed Client at Bangalore.
JD for RTL Verification
No Of positions:- 25
Location :- Noida
Exp :- 2-5 yrs
Engineering process and methodologies. Exposure to the complete lifecycle of ASIC Flow is essential. Interface with the engineering team to gather requirements. Improves process and tools methodologies (as needed).creates requirement documents/SOW for the development team communicates effectively with the stakeholders. Ability to prioritize, plan, coordinate and deliver on multiple tasks/projects simultaneously. Ability to adjust and set priorities to meet deadlines. Proficient in hands on SOC Design methodologies. Create manage and track project deliverables including but not limited to:
Job Description
Frontend design/verification
Directed processor based (assembly/C) based verification
Exposure Arm processors
APB/AHB/AXI protocol understanding
Understanding & exposure to SoC verification env and standard peripheral knowledge.
Code coverage analysis and closure
Behavioral model & Test bench development
Random verification (Added advantage)
System Verilog coding
BFM/Scoreboard development
VMM/OVM/UVM methodology understanding
Functional coverage driven verification
Working with Standard tools NCSIM, VCS
Gate level simulation/debug
Scripting language exposure
Minimum Experience
2+ years with demonstrated experience in project management in VLSI Design Flow. Possesses sufficient technical competency to participate in and add value to program and technical discussions and resolving issues.
Excellent verbal and written communications skills. Excellent team interface skills and the ability to work under tight timelines excellent analytical skills good understanding of technical knowledge, engineering language, and acronyms must function self-sufficiently with little direct supervision
