About the company Ambiq is on a mission to enable intelligence everywhere — powering the AI edge revolution with the world's lowest-power semiconductor solutions. Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010, we've shipped over 300 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications. Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore. We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology. We're looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency. At Ambiq, we live by five values: Innovate. Collaborate. Focus. Learn. Achieve. If that's you, join us — the intelligence everywhere revolution starts here. About the role Work closely with foundation IP team and explore Artificial Intelligence (AI)-assisted and self-adaptive memory design techniques that leverage operating-condition awareness to dynamically optimize memory operation for improved performance, power efficiency, and yield. Responsibilities Analyze conventional memory assist techniques and explore how AI/ML-driven learning and optimization can enhance control logic, supply modulation, boosted/negative voltages, and replica/tracking schemes. Investigate AI/ML-based techniques to analyze memory operating conditions, identify failure signatures, and predict robustness across voltage, temperature, process variation, timing, and parasitic effects. Explore self-timed, self-adaptive, and intelligent memory techniques that learn from operating conditions and dynamically optimize assist decisions for improved robustness, power, performance, and yield. Develop AI/ML-assisted monitoring, prediction, and adaptive control techniques for dynamically optimizing memory assist, voltage, timing, and read/write operations. Document, benchmark, and present the proposed self-adaptive memory architecture and key design insights. Requirements Pursuing a BS in EE, CE, Microelectronics, or related field (rising Junior/Senior). Coursework in Digital Integrated Circuits, Analog Circuit Design, VLSI Design, or Semiconductor Devices. Coursework in Machine Learning, Optimization, Data Analytics, Computational Methods or related courses. Basic understanding of CMOS circuit design and IC layout (DRC/LVS) concepts. Working knowledge of Python and basic ML concepts (regression, clustering). Comfort working with large datasets. Strong analytical and problem-solving ability. Nice to have Exposure to layout/schematic tools (Virtuoso, Calibre) or characterization tools (SiliconSmart, PrimeTime, Liberate) Interest in low-power IP for edge AI/IoT Strong passion, eagerness, and curiosity to learn and explore transistor-level circuit design.
