Key Responsibilities
Strategic Orchestration & Alignment
Unified Roadmap Integration: Translate complex product development roadmaps into long-term infrastructure requirements, driving cross-functional alignment between silicon milestones and lab availability.
Stakeholder Management: Act as the primary liaison between hardware engineering, software development, procurement, and lab operations; navigate competing priorities among stakeholders with differing ownership to keep teams synchronized.
Ambiguity Management: Proactively identify project roadblocks and navigate ambiguous environments to push critical-path dependencies to resolution.
Operational Velocity: Drive continuous improvement in infrastructure processes, identifying and removing friction to increase overall engineering velocity.
Operational Oversight & Execution
Strategic Capacity Planning: Lead high-stakes capacity management efforts, forecasting needs for power, rack space, and compute resources to proactively eliminate infrastructure bottlenecks.
Lifecycle Ownership: Oversee the full lifecycle of infrastructure projects—from initial procurement and technical specification through deployment, validation, and transition to operational readiness.
Visibility & Reporting: Drive the development of dashboards and reporting mechanisms to provide real-time visibility into infrastructure health, ensuring data-driven decision-making across the organization.
Vendor & Asset Optimization: Partner with cross-functional leadership to manage technical specifications, equipment lead times, and hardware lifecycles, ensuring a high-performance, cost-effective infrastructure footprint.
Minimum Qualifications
Bachelor’s degree in Computer Science, Engineering, or a related technical field, or equivalent practical experience.
7+ years of experience in Technical Program Management within hardware development, semiconductor, or complex infrastructure environments.
Deep understanding of Software/Hardware Development Lifecycles (SDLC/HDLC), including ASIC development and silicon validation.
Core Competency: Influencing without authority, with a proven ability to align diverse technical teams toward a singular objective.
Core Competency: High-drive/Self-starter attitude, with a relentless focus on delivering results in fast-paced, high-stakes environments.
Proven ability to manage complex, cross-functional projects with multiple high-stakes dependencies.
Exceptional communication skills, with the ability to translate technical infrastructure needs for varied stakeholders.
Proficiency in standard project management methodologies (Agile/Waterfall) and tools (Jira, Confluence).
Preferred Qualifications
Master’s degree in Computer Science, Engineering, or a related technical field.
Direct experience managing development labs, hardware validation environments, or large-scale test infrastructure.
Familiarity with compute infrastructure, high-speed networking, traffic generation systems, and hardware test automation/CI/CD pipelines.
Experience with technical equipment procurement, vendor management, and budget planning.
Strong track record of developing infrastructure observability tools and driving operational excellence across large engineering organizations.
Why Cisco?
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.
