Key Responsibilities
Architecture & Technical Leadership
Define and own the end-to-end electrical architecture for smart cable modules, including SerDes channel topology, power delivery strategy, and thermal budgeting for muti-Gig (112G PAM4 and 56G NRZ ) designs
Establish and maintain internal electrical design standards, PCB layout rules, and SI/PI guidelines that the broader hardware team
Lead technical reviews (architecture, schematic, layout, DVT) and provide authoritative sign-off on high-speed digital designs
Contribute to the module hardware roadmap in alignment with host ASIC platform generations, MSA form-factor evolution, and customer requirements
Evaluate and select components; engage directly with supplier engineering teams on reference design adaptation and silicon bring-up support.
Electrical Design Ownership
Drive schematic capture and PCB design for complex multi-layer modules housing muti-Gig SerDes retimer or DSP ASICs in thermally and spatially constrained OSFP/QSFP-DD enclosures
Own power delivery design including multi-rail regulation, hot-plug sequencing, brownout protection, and inrush management within MSA-defined power envelopes.
Review and recommendation on PCB stack-up, impedance targets, via structures, and differential-pair routing rules; review and approve layout execution with sufficient SI understanding to ensure first-pass compliance
Define module management hardware architecture: I2C topology, register map implementation, microcontroller selection, and diagnostic monitoring interface circuitry
Perform analog and mixed-signal sub-circuit design including clock distribution, oscillator selection, ESD protection, and supervisory logic
Validation & Bring-Up Leadership
Author/co-author hardware bring-up strategies, debug plans, and acceptance test procedures for new module designs; lead or directly execute board bring-up.
Oversee firmware integration testing, control-interface validation, and module diagnostic monitoring verification
Lead root-cause analysis on complex hardware failures; review failure analysis reports and implement changes.
Define and champion DFT/DFM strategies with CM and PCB fabrication partners to improve yield and reduce manufacturing cost
Cross-Functional & Organizational Impact
Collaborate with firmware and software teams to define initialization sequences, power management schemes, and real-time diagnostic algorithms
Represent the organization in relevant MSA, and IEEE standards working groups; influence specification development in support of company product strategy
Mentor and technically develop senior and mid-level engineers; elevate the hardware team's collective capabilities in high-speed design
Contribute to strategic hiring, technical onboarding, and department-level engineering process improvement
Required Qualifications
Bachelor’s or Master’s degree in electrical engineering or closely related field;
10-12+ years of progressive electrical engineering experience, with at least 5 years focused on high-speed SerDes-based interconnect, active copper cable, or optical/pluggable module products
Demonstrated track record of architecting and delivering production hardware with 56G / 112G and faster SerDes interfaces (Ethernet, PCIe, or InfiniBand)
Expert-level understanding of signal integrity principles - impedance control, differential pair management, eye mask budgeting, channel loss allocation - sufficient to author design rules and review layout without performing full SI simulation
Proficiency with EDA tools: industry-standard schematic capture (Cadence Allegro / OrCAD) and PCB layout review
Deep familiarity with OSFP, QSFP-DD800, and SFP-DD MSA mechanical, electrical, and management specifications
Hands-on experience with CMIS 5.x / SFF-8636 module management and I2C/MDIO interface design
Proven ability to lead hardware bring-up and debug complex mixed-signal failures using high-bandwidth oscilloscopes and protocol analyzers
Strong PDN design fundamentals: multi-rail sequencing, transient response, decoupling strategy, and thermal-electrical co-analysis
Experience interfacing with silicon vendors/teams on customizing reference design, silicon errata management, and platform bring-up
Preferred Qualifications
Experience at the architecture or lead engineer level on 800G or beyond module programs
Familiarity with co-packaged optics (CPO) or linear drive (LPO) module electrical architecture
Working knowledge of host-side switching ASIC electrical interfaces and SerDes equalization schemes
Participation in OIF, IEEE 802.3, or QSFP/OSFP MSA standards bodies
Experience with PCIe Gen 5/6 retimer module designs
Scripting fluency in Python for lab automation, measurement data reduction, or hardware characterization workflows
Base salary range is $185,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
