This is a critical leadership position with high impact on first-pass silicon success and production quality for next-generation AI connectivity solutions.
Key Responsibilities
DFT Architecture & Technical Leadership
Define and own DFT architecture for complex SoCs, including Scan, MBIST, LBIST, JTAG/iJTAG, and ATPG strategies
Lead DFT planning, specification, and quality tracking across the project lifecycle
Provide technical leadership and drive DFT sign-off readiness to ensure successful tapeout
Execution Across the Full Lifecycle
Lead DFT implementation, integration, and verification at block, full-chip and chiplet levels
Own end-to-end DFT activities from specification through silicon bring-up and production support
Ensure high test coverage, robust pattern generation, and alignment with manufacturing requirements
Methodology & Cross-Functional Impact
Develop and drive scalable DFT methodologies, flows, and automation frameworks
Collaborate closely with RTL, Physical Design, STA, and Test Engineering teams to ensure design-for-test readiness
Optimize DFT integration across front-end and backend flows to improve quality, PPA, and turnaround time
Basic Qualifications
Bachelor’s degree in Electrical Engineering or related technical field (Master’s preferred)
12+ years of experience in DFT design, implementation, and verification for complex ASIC/SoC designs
Proven experience in leading DFT activities across full chip development cycles
Deep expertise in DFT techniques including Scan, MBIST, LBIST, JTAG/iJTAG, and ATPG
Strong understanding of DFT and Physical Design flows, including timing implications and integration challenges
Experience with industry-standard DFT tools (Siemens Tessent, Synopsys TestMAX or equivalent)
Solid experience with DFT verification methodologies and coverage analysis
Strong scripting skills (Tcl, Python, or Perl) for automation and flow development
Preferred Qualifications
Experience with advanced process nodes (7nm and below)
Background in high-speed connectivity designs (PCIe, Ethernet, CXL, or similar)
Experience with hierarchical DFT methodologies and large multi-die or chiplet-based systems
Knowledge of silicon bring-up, production test flows, and yield optimization
Familiarity with STA, low-power design, and CDC as it relates to DFT integration
Strong leadership and communication skills, with ability to influence cross-functional teams globally
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
