Develop and execute verification strategies for IP, subsystem, and SoC designs.
Verify CPU, PCIe, DDR, Security, coherency, memory subsystem, and interconnect functionality.
Perform power-aware verification and system scenario/performance validation.
Own verification deliverables from planning through verification closure while ensuring quality, schedule, and execution commitments are met.
Architect, develop, and maintain reusable verification environments, verification IPs, methodologies, and automation.
Develop verification plans, test methodologies, test cases, and coverage closure strategies.
Drive functional, code, toggle, assertion, and coverage closure.
Debug RTL, testbench, integration, and system-level issues.
Collaborate with architecture, design, firmware, emulation, FPGA, validation, and post-silicon teams.
Leverage automation, scripting, and AI-assisted workflows to improve verification productivity.
Contribute to methodology improvements, documentation, and engineering best practices.
Required Skills and Qualifications
Bachelor's or Master's degree in a relevant engineering discipline.
10+ years of IP, subsystem, or SoC verification experience.
Strong Verilog, SystemVerilog, UVM, and modern verification methodologies.
Experience with Arm-based SoC architecture, coherency, interconnects, memory hierarchy, and UPF.
Experience with C/C++, scripting, coverage closure, and strong RTL/testbench debug.
Excellent analytical, communication, and collaboration skills.
Desired Skills and Qualifications
Experience with CHI, ACE, AMBA, PCIe, DDR, or Security IP.
Arm System Architecture knowledge.
Assembly programming.
Formal verification, emulation, FPGA, gate-level simulation, or post-silicon validation.
AI-assisted verification and globally distributed engineering experience.
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