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Texas Instruments is seeking Design Verification Engineer. In this role you will confirm the accuracy of designs for analog and mixed signal electronic parts, components, or integrated circuitry for analog and mixed signal electronic equipment and other hardware systems before pattern generation/mask development. The role will require working independently from the product development team who designed the devices to confirm adherence to known design rules, procedures, and best practices. You will be required to undertake complete ownership of IP/Full chip DV ownership right from spec definition till the post silicon verification and solving the customer issues on need basis.
This includes
Active involvement with architecture team during the spec definition phase
Verification strategy definition along with Verification plan to meet 100% spec to regression traceability along with signoff metrics
ip/Full chip verification covering functional and firmware scenarios in RTL and GLS.
DV Environment ownership: TB development/enhancements including checkers and coverage monitor definitions along with DV flow updates as per the project needs. Develop and maintain comprehensive verification environments using UVM
Active collaboration with cross functional teams - Architecture, RTL, PD, DFT, Systems, Analog, FW and Application teams to ensure comprehensive verification of specific IP/Subsystem/SOC starting from spec definition till post silicon verification closure activities
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Minimum requirements
Minimum of 5+ years of experience in Digital Design Verification. with a Bachelor or master’s degree in EE/ECE/CS or related specializations
Excellent debugging skills with SystemVerilog/VHDL/VAMS designs, with understanding of testbench creation for full chip solutions.
Must have good understanding of analog concepts to create behavioral models for Analog IPs in System Verilog, needed for signal chain verification.
Experience in Motor control for BLDC/BSM motor driver devices including commutation, sensor less control and feedback systems are an added advantage.
Well versed with setting up nad debugging, Gate level simulations/Formal verification methodologies.
Good knowhow of cadence tools for Design verification activities is an advantage.
Preferred qualifications
Ability to establish strong relationships with key stakeholders critical to success, both internally and externally
Strong verbal and written communication skills
Ability to quickly ramp on new systems and processes
Demonstrated strong interpersonal, analytical and problem-solving skills
Ability to work in teams and collaborate effectively with people in different functions
Ability to take the initiative and drive for results
Strong time management skills that enable on-time project delivery
