Metrology & Yield Improvement: Utilize advanced metrology (CD-SEM, Overlay, Scatterometry) to identify defects and improve Critical Dimension Uniformity (CDU) and overlay performance.
Vendor & Subsystem Interaction: Work with equipment vendors to evaluate new materials, photoresists, and tool hardware upgrades.
Data Analysis & SPC: Analyze process data, identify root cause, and implement robust process improvements. Apply Statistical Process Control (SPC) and Design of Experiments (DOE) to develop new processes to enable Litho shrink processes.
Pathfinding & Technology Transfer: Define pathfinding activities for new patterning technology, evaluating High NA Immersion for next-generation nodes. Lead technology transfer from R&D to HVM for photolithography processes.
Photo Process Characterization: Lead development to create next generation Litho Shrink processes for 20nm class logic nodes.
Drive litho-etch integration (LE, LELE, SADP / pitch doubling) for advanced patterning schemes.
Develop and implement resolution enhancement techniques (RET) and optical proximity correction (OPC)strategies.
Evaluate and select materials systems, including photoresists, hard masks, and anti-reflective coatings.
Characterize and reduce patterning defects, including line edge roughness (LER), CD variation, and overlay errors.
Collaborate closely with Etch team to optimize pattern transfer, profile control, and CD uniformity Interface with cross-functional teams including design, integration, yield, and manufacturing.
Minimum requirements
Master's in Electrical Engineering, Materials Science, Physics, or related discipline
5+ years of industry experience in advanced semiconductor process development
Direct, hands-on experience with 22nm node or comparable advanced nodes (e.g., 28nm, 14nm)
Strong expertise in
Photolithography process development and optimization
Litho-etch integration (LELE, SADP, pitch splitting/doubling)
OPC and Resolution Enhancement Techniques (RET) methodologies
Dry etch processes for pattern transfer
Deep understanding of
Critical dimension (CD) control and uniformity
Overlay and alignment challenges
Defectivity mechanisms and mitigation strategies
Preferred qualifications
PhD in Electrical Engineering, Materials Science, Physics, or related discipline
Experience with self-aligned multiple patterning (SAMP, SADP, SAQP)
Familiarity with advanced nodes below 22nm (e.g., 16/14nm FinFET technologies)
Experience working in high-volume manufacturing environments (foundry or IDM)
Exposure to industry-standard modeling and OPC tools
Strong problem-solving skills with a data-driven approach
Demonstrated ability to work cross-functionally in fast-paced environments
Experience with advanced reticle layout and Resolution Enhancement Techniques (RET)
Demonstrated strong analytical and problem-solving skills, with a collaborative team-player mindset
Technical Skills: Deep understanding of Immersion lithography, DUV, and multi-patterning processes. Demonstrated ability to Design for Manufacturing
Software Skills: Proficiency with lithography simulation software (ProLith, S-Litho) and data analysis tools (e.g., JMP, Python)
