Minimum requirements
Masters in Electrical Engineering, Physics, Computer Science, Chemistry or related degree
5+ years experience in a semiconductor photolithography and/or OPC development
Lithography & RET expertise for 45nm, 28nm, 22nm or 20nm processing nodes
Hands-on experience handling high-volume SEM measurement data and image inspections
Strong layout review skills using OPC verification tools to determine and isolate critical metrology targets
Profound understanding of OPC development flows, process window optimization, and design rule constraints
Preferred qualifications
Strong knowledge/understanding of advanced lithography processes, lithography simulation techniques, mask making and RET techniques used in semiconductor manufacturing and process development
Demonstrated leadership skills with the ability to influence cross-functional teams and effectively communicate technical requirements to manufacturing staff on the Fab floor
Familiarity with physical layout (gds/oas). Knowledge of litho/OPC test pattern design and layout execution using test pattern generators and use of layout software like Virtuoso, KLayout
Programming experience in Unix environment
Understanding of OPC pattern validation methodologies and process window assessment techniques like KLA’s Photolithography Wafer Qualification (PWQ)
Demonstrated strong analytical and problem solving skills
Strong verbal and written communication skills
Ability to work in teams and collaborate effectively with people in different functions
Strong time management skills that enable on-time project delivery
Demonstrated ability to build strong, influential relationships
Ability to work effectively in a fast-paced and rapidly changing environment
Ability to take the initiative and drive for results
