Participating in layout design reviews
Creating design flow automation
Texas Instruments will not sponsor job applicants for visas or work authorization for this position.
Minimum requirements
Currently pursuing an Associates or Bachelors degree in Electrical Engineering, Engineering Technology, or related degree
Minimum 3.0 out of 4.0 GPA
Preferred qualifications
Working knowledge of electrical circuits such as resistance, capacitance, voltage and current
Familiarity with Unix/Linux, Cadence Virtuoso, Assura LVS, DRC, or similar mixed signal EDA tools (Mentor, Synopsys)
Basic proficiency in one or more coding languages such as Perl, Python, C, Cadence SKILL
Familiarity with semiconductor device physics, analog circuits and their layout sensitivities
Working knowledge of semiconductor processes and IC production flow including BJTs, Diodes, FETs, passive components, packaging and thermal design
Working knowledge of layout-related matching techniques, on-chip parasitic sources and minimization, routing impedances and electromigration, and crosstalk
Ability to establish strong relationships with key stakeholders critical to success, both internally and externally
Strong verbal and written communication skills
Ability to quickly ramp on new systems and processes
Demonstrated strong interpersonal, analytical and problem-solving skills
Ability to work in teams and collaborate effectively with people in different functions
Ability to take the initiative and drive for results
Strong time management skills that enable on-time project delivery
Put your talent to work with us as a Layout Design Intern– change the world, love your job!
