Contribute to the development of design rules and patterning strategies for advanced nodes (e.g., 28nm, 22nm).
Mentor junior engineers and contribute to knowledge sharing within the team.
Minimum Qualifications
Master's in Electrical Engineering, Physics, Materials Science, or a related field.
5+ years of experience in design retargeting, OPC, or physical design in a semiconductor or EDA environment.
Strong understanding of optical lithography principles, RET (e.g., OPC, SRA, assist features), and mask technology.
Hands-on experience with industry-standard OPC software tools (e.g., Synopsis Sentaurus Lithography, Mentor Calibre, ASML Brion).
Proficiency in scripting with any scripting languages
Familiarity with layout editing and verification tools (e.g., Calibre, Virtuoso, ICC2).
Understanding of lithography, patterning, and process integration challenges in advanced nodes.
Familiarity with 28nm and below.
Preferred Qualifications
PhD in Electrical Engineering, Physics, Materials Science, or a related field.
Solid knowledge of semiconductor device physics and fabrication processes.
Experience in analog layout interaction with lithography and OPC flows.
Experience with statistical data analysis and yield improvement methodologies.
Strong analytical and problem-solving skills.
Ability to work effectively in a cross-functional team environment.
Excellent problem-solving, analytical, and communication skills.
Knowledge of design rule checking (DRC) and layout versus schematic (LVS).
Knowledge of Design Technology Co-Optimization (DTCO)
Exposure to machine learning or data-driven approaches for layout optimization.
