Security: Define scalable Hardware Security Module architectures spanning low-to-mid-to-high segment products. Own crypto IP selection and integration, secure boot architecture, key management, and certification strategy (ISO 21434, IEC 62443). Drive Caliptra support and reusable security software driver frameworks.
Communications & Audio: Architect high-speed and low-power communication IP blocks including USB, Ethernet, CAN-FD, LIN, and audio subsystems. Define interface specifications, PHY integration strategies, and protocol compliance requirements for industrial and automotive applications.
Networking: Lead IP architecture for on-chip networking fabrics, Ethernet switch subsystems, TSN (Time-Sensitive Networking), and functional safety-aware interconnects. Define QoS, traffic shaping, and real-time determinism requirements for industrial automation and automotive networking.
Control & Sense: Own architecture of analog-digital interface IP including ADCs, DACs, comparators, timers, PWM engines, and sensor interface blocks. Define mixed-signal integration strategies, calibration architectures, and functional safety (IEC 61508 / ISO 26262) compliance for motor control and industrial sensing applications.
Platform & Infrastructure: Define the foundational SoC infrastructure IP: power management, clock/reset distribution, DMA engines, memory controllers, debug/trace subsystems, and boot infrastructure. Drive reuse strategies and platform IP standardization across product families.
Key Responsibilities
Own the end-to-end architecture and IP roadmap for your assigned domain vertical, from concept through silicon delivery.
Define architectural requirements and micro-architecture specifications for IP blocks; lead trade-off analysis across PPA (Power, Performance, Area) vectors.
Translate high-level market and system requirements into implementable HW and SW feature definitions.
Assess cost, power, security, and functional safety implications of architectural choices at the IP and SoC level.
Drive IP reuse strategy across multiple SoC platforms
Engage with external IP vendors, standards bodies, and ecosystem partners as needed.
Represent the vertical in cross-functional planning forums and communicate architectural vision to senior leadership.
Minimum requirements
8–15 years of relevant experience in SoC architecture, IP design, or digital/mixed-signal design.
Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
Demonstrated expertise in at least one of the IP domain verticals listed above.
Strong understanding of SoC architecture principles: system partitioning, bus fabrics, power domains, clock/reset, and memory subsystems.
Proven ability to define architectural specifications and lead IP development from concept to tape-out.
Experience with ARM Cortex-M/R/A processor families and/or RISC-V architectures.
Solid foundation in hardware/software interface design and embedded system integration.
Strong analytical and problem-solving skills with the ability to make sound judgments based on early or partial data.
