Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL , Ethernet, NVLink, PCIe , and UALink semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. As an Astera Labs Technical Lead Physical Design Engineer you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This role requires end-to-end STA ownership across design stages, deep technical expertise, and close collaboration with RTL, physical design, and verification teams to ensure robust full-chip timing convergence. This role is fully on-site and in-person. Responsibilities Drive timing closure from RTL through sign-off, ensuring robust timing across complex SoCs. Develop and validate SDC constraints, including MMMC setup, to enable accurate and efficient STA analysis. Define and manage I/O timing budgets across hierarchical designs. Apply advanced sign-off methodologies at TSMC 7nm and below, including OCV/AOCV and PVT effects. Leverage ETM libraries for hierarchical timing analysis and correlation, balancing runtime and accuracy. Provide actionable timing feedback at both block and full-chip levels, including root cause analysis and ECO guidance. Manage large-scale multi-corner/multi-mode STA runs with automation, partitioning, and efficient resource usage. Generate and validate timing ECOs, partnering with physical design and RTL teams for quick closure. Partner closely with design, implementation, and verification teams to drive timing convergence, providing sign-off level expertise and guidance. Requirements Bachelor’s in Electrical Engineering or Computer Science required; Master’s preferred. ≥5 years of experience in timing analysis and sign-off for complex SoCs in Server, Storage, or Networking applications. Expertise in timing constraints, STA methodology, and timing closure at both block and full-chip level. Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below). Proficiency with Cadence and/or Synopsys physical design/STA toolchains. Strong scripting ability (Tcl, Python, Perl). Ability to work independently with strong prioritization and a professional, customer-focused mindset. Nice to have Familiarity with high-speed SERDES and Ethernet PHY timing challenges. Knowledge of ECO methodologies, DFT tools, and test coverage analysis. Experience working with IP vendors for both RTL and hard-macro integration. SystemVerilog/Verilog familiarity. The base salary range is $140,000 CAD – $180,000.00 CAD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
