Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL , Ethernet, NVLink, PCIe , and UALink semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. About the role Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Senior ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects. As a Senior ASIC Design Engineer, you won't just build chips—you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity. Responsibilities Design Ownership & Implementation Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams Quality Assurance & Design Optimization Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient Apply design techniques to meet PPA (Power, Performance, Area) targets Contribute to design quality through verification and validation activities Methodology Innovation & Collaboration Participate in design methodology improvements and tool automation initiatives Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter Collaborate effectively across teams to ensure seamless integration Requirements Bachelor's degree in Electrical Engineering or related technical field 3+ years of experience in logic design at semiconductor companies Knowledge and experience in Verilog and/or SystemVerilog Excellent communication skills with ability to work effectively across teams Understanding of digital design principles and RTL coding best practices Nice to have Master's degree in Electrical Engineering or related field Knowledge of DDR and PCIe protocols and implementation Understanding of power management techniques for low-power design Familiarity with Clock Domain Crossing, simulation, debugging, synthesis, and timing analysis Proficiency in scripting languages such as Python or Perl Experience with high-speed serial interface designs or connectivity protocols We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
