Developing and Executing Verification Testcases: Create comprehensive testcases using SystemVerilog and UVM methodologies to verify complex digital designs, including constrained-random testing scenarios and functional coverage analysis.
Simulation and Debugging: Run simulations using industry-standard EDA tools, analyze results, and debug design issues to identify and resolve functional problems, contributing to improved product quality and reliability.
Testbench Development: Assist in building and enhancing verification environments and testbenches, implementing verification IP (VIP) for various protocols such as PCIe, UCIe, DDR, AXI, APB, AHB, and other industry-standard interfaces.
Coverage-Driven Verification: Develop functional coverage models and analyze coverage metrics to ensure comprehensive verification of design features, helping to reduce design risk and accelerate project execution.
Collaboration and Learning: Work closely with design, verification, and validation teams to understand product architecture, verification flows, and methodologies, while contributing fresh perspectives and innovative solutions to technical challenges.
What You'll Need
Required Qualifications
Currently pursuing a degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or related technical discipline.
Basic understanding of Digital Design fundamentals, including combinational/sequential logic, finite state machines (FSM), clocking, and reset concepts.
Knowledge of Verilog/SystemVerilog for RTL design and verification.
Familiarity with design verification methodologies, preferably UVM (Universal Verification Methodology) concepts.
Understanding of verification techniques such as testcase development, constrained-random testing, functional coverage, and debugging.
Familiarity with Linux/Unix operating environments and simulation tools.
Strong analytical and problem-solving skills with the ability to investigate and debug complex technical issues.
Good communication skills, both written and verbal, to effectively collaborate with design, verification, and validation teams.
Ability to work independently as well as in a team-oriented environment.
Preferred Qualifications
Experience with assertion-based verification (SVA) and coverage-driven verification techniques.
Knowledge of scripting languages such as Python, Perl, Shell, or TCL.
Familiarity with version control systems like Git.
Understanding of industry-standard protocols such as PCIe, UCIe, DDR, AXI, APB, AHB, SPI, I2C, or UART.
Experience with FPGA or hardware verification projects.
Key Program Facts
Program Length: December 2026 – May 2027 (6 months)
Location: Vietnam (Ha Noi - VN10)
Working Model: Onsite
Full-Time/Part-Time: Full-Time
Start Date: December 2026
Equal Opportunity Statement
Synopsys is committed to creating an inclusive workplace and is an equal opportunity employer. We welcome all qualified applicants to apply, regardless of age, color, family or medical leave, gender identity or expression, marital status, disability, race and ethnicity, religion, sexual orientation, or any other characteristic protected by local laws. If you need assistance or a reasonable accommodation during the application process, please reach out to us.