Synopsys
From Synopsys's careers page
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At Synopsys, you will work on memory interface IP that powers the next generation of AI accelerators, data centers, and high-performance compute.
Job Title
Sr. Staff Digital Design Engineer - Memory Interface IP- HBM/DDR/LPDDR
We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You have spent years designing ASICs that move data at speeds most people cannot fathom, and you understand that memory interface IP is where performance lives or dies. HBM, DDR, LPDDR are not just acronyms to you, they are architectures you have debugged at 2 a.m., optimized for power and timing, and shipped into production silicon that someone is using right now. You know the difference between a design that meets spec on paper and one that actually works in the lab when the signal integrity issues show up.
You do not need someone to tell you what good RTL looks like. You have written enough of it to know when a module is going to cause problems three months from now, and you speak up before it gets there. Working across analog, physical design, and applications teams does not slow you down, it is where you do your best work because you understand that great IP is built at the intersections.
At Synopsys, you will work on memory interface IP that powers the next generation of AI accelerators, data centers, and high-performance compute. The problems are hard, the stakes are real, and the team expects you to lead.
Design and own complex RTL blocks for HBM, DDR, and LPDDR memory interface IP, from architecture through implementation and verification handoff
Collaborate directly with analog design teams to define and validate mixed-signal interfaces, ensuring timing closure and signal integrity across the full IP stack
Develop and execute detailed verification plans in partnership with the verification team, including corner case analysis and protocol compliance testing
Drive timing, power, and area optimization using industry-standard EDA tools like Synopsys Fusion Compiler, PrimeTime, and DC Compiler
Lead technical reviews and design audits, providing clear direction on architecture tradeoffs and implementation risks
Mentor engineers on the team, reviewing RTL code, guiding design decisions, and helping them build the judgment that separates working designs from great ones
Interface directly with customer engineering teams to debug integration issues, answer technical questions, and ensure successful IP deployment in their SoCs
The Impact You Will Have
Deliver memory interface IP that enables customers to hit their performance and power targets in AI, automotive, and data center applications
Reduce integration risk and time-to-market for customers by designing IP that works correctly the first time in silicon
Set the technical standard for RTL quality, verification rigor, and design methodology across the IP development team
Solve hard problems at the boundary of digital and analog design that directly affect whether a multi-billion transistor chip tapes out on schedule
Build the next generation of design talent at Synopsys by mentoring engineers and raising the bar on what good design looks like
Contribute to Synopsys' position as the go-to provider for high-speed memory interface IP in the most demanding applications on the planet
Shape the roadmap for future memory interface IP by bringing deep technical insight from customer engagements and silicon bring-up back into the product
6 - 8+ years of hands-on ASIC digital design experience with a strong focus on RTL design and verification
Deep expertise in at least two of the following memory interface protocols: HBM, DDR4, DDR5, LPDDR4, LPDDR5
Proven experience designing and delivering production-quality IP or SoC blocks that have taped out and been validated in silicon
Strong command of SystemVerilog for RTL design and familiarity with UVM or other verification methodologies for cross-functional collaboration
Experience working with AMBA protocols (AXI, AHB, APB) in the context of memory subsystem integration
Proficiency with Synopsys or Cadence EDA toolchains for synthesis, timing analysis, and power optimization
Experience with mixed-signal interface design and collaboration with analog teams is a strong plus
You can walk into a design review, spot the architectural flaw that will cause a problem in six months, and explain it clearly enough that the team course-corrects without drama
You write RTL that other engineers want to read, not because it is clever, but because it is clear, maintainable, and does exactly what it needs to do
When a customer reports a timing violation or protocol issue, you do not wait for a full repro, you start narrowing down the root cause and working the problem
You are comfortable making technical calls with incomplete information, and you are equally comfortable changing your mind when new data shows up
Mentoring is not a checkbox for you, you genuinely care about helping less experienced engineers get better, and you know how to give feedback that sticks
You stay current on memory standards, EDA tool updates, and industry trends because you know that what worked two years ago might not be the right answer today
The Team You'll Be Part Of
You will be part of a highly skilled ASIC Digital Design team focused on delivering high-performance memory interface IP. The team works closely with analog design, physical design, and applications engineering to ensure seamless integration and successful customer deployments. This is a team that values technical depth, clear communication, and continuous improvement.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
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