Develop, validate, and maintain timing constraints (SDC) including clocks, generated clocks, exceptions, IO constraints, and mode/corner coverage.
Run and analyze power signoff/support flows (PrimePower / PT-PX) and correlate timing/power impacts of ECOs.
Support timing and power ECO generation, and validate fixes through signoff checks and regressions.
Work with synthesis/implementation teams to ensure tool correlation and correct interpretation of constraints and physical effects (parasitics, SI awareness, AOCV/POCV, derates).
Use Synopsys tools such as PrimeTime, PrimePower/PT-PX, PrimeClosure/Tweaker (as applicable) to meet PPA targets.
Build/maintain automation in TCL/Python/Perl to improve STA productivity, reporting, and regression quality.
Contribute to improving STA methodologies, checklists, and best practices; mentor junior engineers informally as needed.
The Impact You Will Have
Enable predictable and high-quality timing closure for high-performance, low-power silicon.
Improve first-pass success through robust constraints, clean signoff, and disciplined closure practices.
Strengthen team execution by contributing to repeatable STA flows, automation, and cross-team alignment.
Support successful project milestones through timely analysis, crisp communication, and ownership of deliverables.
What You’ll Need
Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics/Electrical Engineering or related field.
8+ years of relevant experience in STA / timing closure (block ownership expected; full-chip exposure preferred).
Strong hands-on experience in
Constraints development/validation (SDC)
STA signoff across modes/corners, including MMMC concepts
Timing closure debugging and ECO validation
Power analysis/support (PrimePower / PT-PX exposure preferred)
Proficiency with Synopsys tools such as PrimeTime (required); PrimePower/PT-PX, PrimeClosure/Tweaker (preferred).
Working knowledge/exposure to Fusion Compiler/ICC2 or DC, parasitic extraction concepts (e.g., StarRC), and signoff correlation (preferred).
Strong scripting skills in TCL (required) and Python/Perl (preferred).
Understanding of low-power and high-frequency design considerations (UPF awareness is a plus).
Who You Are
Self-driven, accountable, and comfortable working with minimal supervision on defined deliverables.
Strong analytical and debugging skills with attention to detail.
Clear communicator and effective collaborator across design, PD, and verification.
Open to learning, improving flows, and sharing knowledge within the team.
The Team You’ll Be A Part Of
You’ll join a team of backend and STA engineers focused on delivering robust timing and power closure solutions for leading silicon designs. The team values technical rigor, collaboration, and continuous improvement—working closely with experts across domains to help customers achieve their silicon goals.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share details on compensation and benefits during the hiring process.
