Synopsys
From Synopsys's careers page
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We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You are a seasoned RTL design leader with a strong record of driving complex ASIC digital subsystems from concept to silicon. You bring the technical depth to define architecture, translate requirements into clear specifications, and deliver high-quality, first-time-right RTL for robust, scalable subsystem designs.
Your background includes multiple successful tape-outs and deep experience working across design, verification, DFT, and implementation to bring complex programs to closure. You are fluent in industry-standard protocols such as UCIe, Ethernet, UALink, and AMBA, and you apply strong judgment in low power design, DFT architecture, and subsystem-level technical decision-making.
Leading the subsystem lifecycle from requirements and architecture definition through release
Developing subsystem architecture, functional specifications, and high-quality RTL micro-architecture
Driving design quality through RTL linting, CDC, RDC, and close partnership with verification, DFT, and implementation teams
Integrating standard protocols such as UCIe, Ethernet, UALink, and AMBA into subsystem designs
Applying low power and DFT design methodologies at the architectural level
Mentoring junior engineers and contributing to technical reviews and design excellence
Delivering high-performance digital IP subsystems that power next-generation silicon solutions
Enabling first-time-right RTL, helping reduce verification cycles and accelerate time-to-market
Strengthening subsystem quality, scalability, and interoperability through rigorous design practices
Influencing architectural decisions that shape the future of digital IP design at Synopsys
Contributing to a collaborative, innovative engineering culture through mentorship and technical leadership
BSEE, BSCE, MSEE, MSCE, or an advanced degree, plus 8+ years of direct experience in RTL design and subsystem architecture for complex ASIC or SoC projects
Strong expertise in RTL coding using Verilog/System Verilog, along with linting, CDC, RDC, and formal verification tools
Experience with standard protocols such as UCIe, Ethernet, UALink, and AMBA
Solid knowledge of low power design methodologies, DFT architecture, and the broader ASIC design flow
Proven ability to lead cross-functional efforts from specification through silicon
A strong technical leader with a growth mindset and a commitment to continuous learning
A clear communicator who can work effectively across diverse technical teams
A collaborative mentor who helps raise the performance of those around you
Analytical, detail-oriented, and driven to solve complex design challenges with quality and rigor
Adaptable and resilient in a fast-moving, high-performance environment
You will join the Synopsys Digital IP Subsystem team, a group focused on delivering high-performance, reliable, and scalable digital subsystems for global customers. The team values technical excellence, collaboration, and innovation, and plays an important role in advancing Synopsys leadership in engineering solutions from silicon to systems.
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring proTop of Form
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