Innovating solutions to problems independently, with occasional guidance.
Setting task-level goals and consistently meeting schedules.
Collaborating with other Synopsys teams, including BU AE and Sales, to broaden and deploy tool and IP solutions.
Providing technical guidance and mentorship to junior team members
The Impact You Will Have
Enhancing the efficiency and effectiveness of SOC design processes.
Driving innovation in chip design and verification methodologies.
Ensuring the successful deployment of Synopsys' EDA tools and IP solutions.
Improving customer satisfaction through expert advisory and technical support.
Contributing to the development of high-performance silicon chips and software content.
Supporting the continuous technological advancements at Synopsys
What You’ll Need
BS/MS/PhD in Electronics Engineering, Electromechanics, or Telecommunications.
8 to 12 years of hands-on experience in Place & Route domains using Fusion Compiler/ICC2 tool.
Strong debugging skills and a good understanding of P&R, extraction, timing, IREM, and Physical Verification fundamentals.
Experience with signoff tools like PT, Redhawk, StarRC, ICV is an advantage.
Proficiency in TCL/PERL scripting.
Who You Are
Innovative problem solver with the ability to work independently and as part of a team.
Effective communicator with strong English language skills.
Mentor and leader capable of guiding junior team members.
Collaborative team player who can work with cross-functional teams.
Detail-oriented professional with a focus on meeting schedules and goals.
The Team You’ll Be A Part Of
You will be an integral part of our SOC Engineering team, which focuses on developing and implementing advanced SOC designs using Synopsys EDA tools and IP. The team collaborates closely with other Synopsys teams, including Business Units and Sales, to deliver innovative solutions that drive the future of technology.
