We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You have spent over a decade building verification environment that catches the bugs that matter, not just hit coverage targets. You can architect a UVM environment from scratch, write the sequences that stress the design.
At Synopsys, you will work on interface IP that powers real silicon, and the verification environment you build will be the reason it works.
What You'll Be Doing
- Collaborate with design teams to define verification requirements and translate specs into test plans that cover functional, edge case, and performance scenarios
- Architect and implement UVM testbench environments, including agents, scoreboards, and reusable verification components for interface IP designs
- Write System Verilog test sequences and constrained random stimulus to stress designs and uncover corner cases before silicon
- Implement System Verilog Assertions for simulation-based functional verification and formal verification flows
- Build and analyze functional and code coverage metrics, identify gaps, and drive coverage closure
- Lead and mentor a team of verification engineers, teaching UVM methodology, debugging techniques, and testbench architecture best practices
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- The Impact You Will Have
- Deliver verified interface IP designs that meet tape out schedules and quality targets, directly enabling customer success in high-performance silicon
- Reduce verification cycle time and improve bug detection through well-architected testbenches and reusable verification IP
- Establish verification standards and methodologies that scale across multiple projects and teams
- Accelerate team productivity by mentoring engineers on UVM, formal verification, and advanced debugging techniques
- Catch critical design issues early in the development cycle, reducing costly respins and improving time to market
- Build verification environments that become reference implementations for future projects
What You'll Need
- Bachelor's or master’s degree in computer engineering, Electrical Engineering, or Communication Engineering
- 8+ years of hands-on ASIC design verification experience with strong focus on UVM-based functional verification
- Deep expertise in System Verilog, including advanced testbench architecture, constrained random verification, and coverage-driven verification
- Proven experience implementing System Verilog Assertions for functional and formal verification flows
- Strong programming skills in at least two of: C, System Verilog, TCL, Perl, or Python
