What You'll Be Doing
Lead layout development for next generation DDR and HBM PHY IP across 7nm, 5nm, 3nm, and future nodes using FinFET and GAA process technologies
Drive floorplanning, layout matching, ESD hardening, latch-up mitigation, and PERC/EMIR closure for analog and mixed-signal blocks in high-speed memory interfaces
Own effort estimation, schedule planning, and execution for layout projects, coordinating across design, verification, and customer engagement teams
Mentor junior layout engineers on deep submicron effects, DFM best practices, and advanced layout techniques while challenging senior engineers to deliver higher quality on tighter timelines
Conduct layout reviews, manage quality checks using Calibre and internal flows, and drive LEF generation, bond-pad layout, IO frame design, and release processes
Translate PHY-level customer requirements into actionable layout constraints and work directly with customers to resolve pitch, area, and integration challenges
Stay hands-on, jumping into critical layout tasks when schedules tighten or technical problems require deep expertise to unblock the team
The Impact You Will Have
Your leadership will directly shape the performance, power, and area of memory PHY IP used in flagship SoCs across hyperscale data centers, AI training systems, and mobile platforms
The floorplans and layout techniques you establish will become the foundation for future generations of DDR and HBM IP, influencing how Synopsys scales to next-node technologies
Your mentorship will build a stronger, more capable layout team that can tackle increasingly complex process nodes and customer requirements with less escalation
The quality and turnaround time improvements you drive will accelerate customer tapeouts and reduce costly respins, strengthening Synopsys relationships with top-tier semiconductor companies
Your ability to translate ambiguous customer specs into executable layout plans will reduce integration risk and improve first-pass success rates for memory subsystems
The cross-functional collaboration you foster between layout, design, and verification will break down silos and make the entire PHY development process more efficient
Your hands-on problem solving during critical project phases will keep schedules on track and ensure that hard-won layout optimizations actually make it into silicon
What You'll Need
Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, or related field
8+ years of hands-on layout design experience in deep submicron CMOS technologies, with direct exposure to 7nm or below
Demonstrated ability to lead layout projects from floorplan through tapeout, including effort estimation, resource planning, and cross-functional coordination
Deep technical expertise in layout matching techniques, ESD design, latch-up prevention, PERC/EMIR analysis, DFM rules, LEF generation, and IO frame layout
Strong understanding of FinFET and GAA process effects, including fin quantization, middle-of-line routing constraints, and advanced node design rules
Experience working with memory PHY IP (DDR, HBM, LPDDR, or similar high-speed interfaces) and translating customer requirements into layout constraints is a strong plus
Proficiency with Cadence Virtuoso, Calibre, and other industry-standard layout and verification tools
Who You Are
You can walk into a layout review, spot a matching issue or an EMIR hotspot in thirty seconds, and explain the fix in a way that teaches the engineer something they will use on the next block
When a customer asks for a 10% area reduction with no performance hit, you do not say yes or no immediately, you go back to the floorplan, run the numbers, and come back with two options and the tradeoffs for each
You hold your team to high standards, but you also know when someone is stuck because the problem is genuinely hard versus when they need to dig deeper, and you adjust your coaching accordingly
Schedules slip when dependencies break, you are the person who sees it coming, pulls the right people into a room, and gets the project back on track without drama
You write clear, concise technical summaries that a design lead, a verification engineer, and a customer can all read and understand without needing three follow-up meetings
You stay current on process technology trends, not because it is required, but because you want to know what is coming at 2nm and how it will change the way you approach layout
The Team You'll Be Part Of
You will join the Silicon IP team in Hyderabad, working on DDR and HBM PHY IP development that serves customers across automotive, data center, mobile, and AI markets. This is a cross-functional environment where layout, design, and verification engineers collaborate closely to deliver cutting-edge memory interfaces on aggressive schedules. The team operates globally, with engineering centers across multiple time zones, and you will work with senior technical leaders who have been driving memory IP innovation for years. Your recruiter will share more about the team structure and current project portfolio during the interview process.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
