Apply expertise in static verification using SpyGlass, formal verification with VC Formal, or dynamic simulation using VCS and UVM
Work with R&D to communicate customer needs and reproduce issues
Deliver technical workshops and training on verification technologies
Build trusted relationships with engineering and management at semiconductor companies across Italy and Europe
The Impact You Will Have
Enable customers to catch critical design issues earlier, reducing respins and schedule risk
Accelerate tool deployment by resolving blockers and providing methodology guidance
Influence product roadmaps by surfacing customer requirements
Help close deals by running evaluations that demonstrate value on customer designs
Reduce support escalations by diagnosing issues and providing R&D with context
What You'll Need
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
5+ years in the semiconductor industry at an EDA company or semiconductor design company
Hands-on experience in RTL verification or verification methodology
Strong knowledge in static verification (SpyGlass), formal verification (VC Formal), or dynamic simulation (VCS, UVM)
Proficiency in Verilog and SystemVerilog
Comfort with Linux and scripting in Tcl, Python, Perl, or shell
Fluent English; Italian language skills are a strong advantage
Who You Are
You listen to a verification problem and walk out with a plan that maps to tool features and methodology changes
You reproduce issues and show up with enough detail that problems can be solved
You present comfortably to engineers who want depth and managers who want to know if this will work
You manage multiple customer engagements without losing track of commitments
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
