What You'll Be Doing
Verify IP blocks and subsystems across DesignWare product lines, developing and executing verification plans, test scenarios, checkers, assertions, and functional coverage models for your assigned areas
Build and enhance UVM-based verification environments that support block-level and subsystem-level testing, regression automation, and coverage closure
Debug complex functional failures across IP domains like Ethernet, USB, PCI Express, or other industry-standard protocols, identifying root causes and driving resolution with design and architecture teams
Analyze regression results, track coverage metrics, and identify gaps or risks that could affect signoff quality or schedule
Write scripts and automation utilities in Python or similar languages to improve debug efficiency, regression analysis, test development, and coverage closure
Collaborate with cross-functional teams including design, firmware, quality, and architecture to clarify requirements, resolve technical issues, and align on verification strategy
Apply AI-assisted techniques where appropriate to accelerate debug workflows, optimize regression cycles, or improve test generation and coverage analysis
The Impact You Will Have
Deliver high-quality, customer-ready DesignWare IP by catching critical bugs early and ensuring thorough verification coverage across your assigned blocks and subsystems
Reduce time-to-signoff by building reusable verification infrastructure, improving regression efficiency, and identifying risks before they become schedule blockers
Strengthen the quality and reliability of Synopsys IP that powers next-generation AI, mobile, automotive, and data center silicon products used by customers worldwide
Enable faster debug and root cause analysis across the team by developing automation tools, sharing technical knowledge, and improving verification workflows
Support predictable project execution by maintaining clear verification plans, tracking progress against coverage and quality goals, and communicating risks early
Contribute to Synopsys leadership in the era of pervasive intelligence by helping verify the IP building blocks that enable advanced AI and compute architectures
Improve team execution and engineering practices through dependable collaboration, peer reviews, documentation, and knowledge sharing
What You'll Need
Bachelor's or Master's in Electrical, Electronics, or Computer Engineering with 5+ years of hands-on IP or SoC verification experience (or MS with 3+ years)
Strong proficiency in SystemVerilog and UVM, VMM, or OVM methodologies, with real project experience developing verification environments, test plans, checkers, assertions, and functional coverage
Hands-on experience with industry-standard simulators such as VCS and associated debug tools, including waveform analysis and regression infrastructure
Demonstrated ability to debug complex functional failures, analyze regression results, track issues to closure, and support verification signoff activities
Experience writing scripts or automation utilities in Python, Perl, or shell to improve verification productivity, debug efficiency, or regression analysis
Practical understanding of verification planning, coverage analysis, quality criteria, and what it takes to reach signoff on real IP or SoC projects
Experience with DesignWare IP or similar synthesizable IP verification projects is a strong plus, as is familiarity with protocols such as Ethernet, USB, or PCI Express
Exposure to AI-assisted methods for debug, regression optimization, test generation, or coverage closure is desirable
Who You Are
You can look at a failing regression and know within 15 minutes whether it is a testbench issue, a design bug, or a corner case no one thought to cover
You write verification code that other engineers can actually understand and reuse six months later without needing to ask you how it works
You push back when a verification plan is too vague or a signoff criterion does not match the actual risk, and you do it in a way that moves the conversation forward
You are comfortable working across time zones and teams, clarifying requirements with architects in one meeting and debugging with design engineers in the next
You do not wait for perfect documentation or complete specs, you ask the right questions, fill in the gaps, and keep moving without creating downstream confusion
You share what you learn, whether that is a debug technique, a coverage trick, or a script that saves the team three hours a week
The Team You'll Be Part Of
Your recruiter will share more about the team structure and mission during the interview process.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
