Lead and mentor a team of verification engineers, teaching UVM methodology, debugging techniques, and testbench architecture best practices
The Impact You Will Have
Deliver verified interface IP designs that meet tape out schedules and quality targets, directly enabling customer success in high-performance silicon
Reduce verification cycle time and improve bug detection through well-architected testbenches and reusable verification IP
Establish verification standards and methodologies that scale across multiple projects and teams
Accelerate team productivity by mentoring engineers on UVM, formal verification, and advanced debugging techniques
Catch critical design issues early in the development cycle, reducing costly respins and improving time to market
Build verification environments that become reference implementations for future projects
What You'll Need
Bachelor's or master’s degree in computer engineering, Electrical Engineering, or Communication Engineering
12+ years of hands-on ASIC design verification experience with strong focus on UVM-based functional verification
Deep expertise in System Verilog, including advanced testbench architecture, constrained random verification, and coverage-driven verification
Proven experience implementing System Verilog Assertions for functional and formal verification flows
Strong programming skills in at least two of: C, System Verilog, TCL, Perl, or Python
Experience with PCI Express and CXL protocols is a strong plus
Experience in interface IP verification, formal verification tools like Jasper or VC Formal, and AI-assisted coding tools like Cursor or GitHub Copilot will set you apart
Who You Are
You can spot a verification gap in a design review that no one else flagged and articulate why it matters in a way that gets it prioritized
You review code with enough precision that engineers know exactly what to fix and enough respect that they want to do better next time
You do not wait for perfect information to start building. You work with what you have, ask the right questions, and move forward
Teaching comes naturally. You can explain UVM factory overrides or coverage bin construction in a way that makes a junior engineer understand it
The Team You'll Be Part Of
Your recruiter will share more about the team structure and mission during the interview process.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
