At Synopsys, you will lead verification for complex ASIC designs that power the products our customers build, and you will do it with a team that values depth, rigor, and getting it right.
What You'll Be Doing
Lead a team of design and verification engineers in Noida, managing performance, growth, and day-to-day execution across multiple ASIC projects
Own the verification strategy and environment architecture for complex, high-speed protocol designs, defining testplans and coverage models that catch real issues
Drive technical decisions around verification flows, including SystemVerilog, UVM, behavioral modeling, and coverage-driven verification
Work directly with architects, RTL designers, and VIP teams to align on design intent, resolve ambiguities, and ensure functional correctness before tapeout
Identify design gaps and propose corrective actions when documented functionality does not match implementation or customer requirements
Reproduce and resolve customer-reported issues through deep technical analysis, working backward from symptoms to root cause
Continuously improve verification methodologies, tooling, and execution efficiency across the team
The Impact You Will Have
Deliver functionally correct, high-performance silicon designs that ship to customers and power next-generation products
Build a team culture where engineers grow technically, take ownership, and solve hard problems without waiting for perfect direction
Reduce time-to-market by catching design issues early through rigorous verification and well-architected testbenches
Strengthen cross-functional collaboration between design, architecture, and verification, ensuring alignment and reducing late-stage surprises
Influence verification best practices across Synopsys, shaping how teams approach coverage, automation, and testbench design
Resolve customer issues faster and more thoroughly, building trust and long-term partnerships
Set the technical bar for what great verification looks like, raising the standard across projects and teams
What You'll Need
15+ years of hands-on experience in ASIC design and verification, with deep expertise in high-speed protocols and complex digital systems
Strong proficiency in Verilog, VHDL, and SystemVerilog for RTL design and verification
Proven experience building UVM-based verification environments, including testbench architecture, coverage analysis, and constraint-driven stimulus
Solid scripting skills in BASH, TCSH, PERL, PYTHON, or TCL for automation, flow development, and productivity tooling
Track record of managing and mentoring engineering teams, balancing technical leadership with people development
Experience working through ambiguous requirements, incomplete specs, or shifting priorities without losing momentum
Who You Are
You can review a verification plan and immediately spot what is missing, whether it is a corner case, a coverage gap, or an unrealistic timeline
You give feedback that makes engineers better, not just feedback that checks a box during a review cycle
You are comfortable saying no when a project plan does not match reality, and you can explain why in a way that moves the conversation forward
You manage multiple projects without losing track of the details that matter, knowing when to dive deep and when to trust your team
You write and communicate clearly in English, whether it is a technical document, a status update, or a difficult conversation with a stakeholder
You adapt quickly when priorities shift, helping your team stay focused on what matters most without creating chaos
The Team You'll Be Part Of
Your recruiter will share more about the team structure and mission during the interview process.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
