- 【仕事内容】
- 最新のSoC向けHBMコントローラIPのRTL設計・実装を担当します。
- 仕様書をもとに詳細なマイクロアーキテクチャを設計します。
- 設計や検証の判断や方針決定、検証計画の策定、テストベンチの構築（SystemVerilog/UVM使用）を行います。
- 設計レビューをリードし、グローバルチームと連携します。
- 若手エンジニアの指導や、進捗・検証レポートの作成も担当します。
- 【期待される成果】
- 高品質なHBMコントローラIPを提供し、AIや自動車、サーバーなど幅広い分野で活躍します。
- 製品の性能向上や統合リスクの低減に貢献し、技術力を高めます。
- チーム全体の技術向上やベストプラクティスを推進します。
- 【必要なスキル・経験】
- RTL設計やマイクロアーキテクチャ設計の経験
- UVM/VMM/OVMなどの検証手法やSystemVerilogの知識
- SoC/ASIC設計フローや検証計画、カバレッジ重視の検証経験
- シミュレーションツール、Unix環境、スクリプト言語（Perl, Python, TCL）
- DDR、PCIE、AXI/CHI、SD/eMMC、Ethernet、USB、MIPIなどのプロトコル知識
- 英語でのコミュニケーション能力
- BSEE（9年以上）またはMSEE（7年以上）の実務経験
- 【歓迎スキル】
- フォーマル検証、ファームウェア・組込みソフト、C/C++、機能安全（ISO26262, FMEDA）経験
What You’ll Be Doing
Designing and implementing RTL-based HBM controller IP cores for cutting-edge SoC applications.
Interpreting and translating standard and product functional specifications into detailed micro-architectures.
Making architectural and methodological judgments for both design and verification activities.
Developing comprehensive verification strategies, including testbench architectures using SystemVerilog and UVM.
Creating and maintaining verification plans, item lists, coverage metrics, and checker definitions to ensure thorough validation.
Coordinating and leading design review meetings to ensure alignment and technical excellence across global teams.
Providing technical leadership and mentoring to junior engineers, setting quality standards and driving innovation.
Documenting progress, generating reports with “visible” verification metrics, and ensuring project milestones are met.
The Impact You Will Have
Delivering high-quality, robust HBM controller IP that accelerates time-to-market for Synopsys customers.
Enabling key innovations for AI, automotive, server, and data center applications through advanced memory interface solutions.
Reducing integration risk and enhancing system performance for a broad portfolio of end-customer products.
Driving technical excellence and best practices across global, cross-functional engineering teams.
Supporting Synopsys’ reputation as a leader in silicon IP by ensuring products meet and exceed industry standards.
Contributing to continuous improvement by identifying and implementing process, methodology, and tool enhancements.
Mentoring and developing the next generation of engineering talent within Synopsys.
What You’ll Need
Extensive hands-on experience with RTL design and micro-architecture development from functional specifications.
Proficiency in verification methodologies (UVM/VMM/OVM), SystemVerilog, and object-oriented verification techniques.
Deep understanding of SoC/ASIC design flows, verification planning, and coverage-driven verification.
Experience with simulation tools, Unix operating environments, and scripting languages (Perl, Python, TCL).
Solid knowledge of protocols such as DDR, PCIE, AMBA (AXI/CHI), SD/eMMC, Ethernet, USB, and MIPI.
Strong English communication skills and the ability to document and present technical concepts effectively.
BSEE with 9~10+ years or MSEE with 7~12+ years of relevant experience.
Advantageous: Experience with formal verification, firmware/embedded software, C/C++, and functional safety standards (ISO26262, FMEDA).
Who You Are
Innovative, self-motivated, and able to work independently with precision.
Exceptional problem-solving skills and keen attention to detail.
Effective communicator and active listener, adept at cross-functional collaboration.
Team-oriented and supportive, with a willingness to mentor and share knowledge.
Adaptable to new challenges, tools, and methodologies in a dynamic environment.
Committed to continuous learning and professional development.
