At Synopsys, you will define the architecture for memory IP that powers AI accelerators, data center processors, and mobile SoCs used by millions of people. The team is global, the problems are hard, and what you design will ship.
What You'll Be Doing
Define and own the digital architecture for HBM, DDR, or LPDDR memory controllers, from high-level partitioning through RTL implementation strategy
Drive design plans for complex memory interface blocks, balancing performance, area, power, and verification complexity across chip and block levels
Collaborate with PHY teams, verification engineers, and product architects to ensure seamless integration and protocol compliance
Evaluate and select design methodologies, tools, and flows that improve quality, reduce cycle time, and scale across product lines
Mentor engineers on architecture decisions, RTL best practices, and debug strategies for high-speed memory interfaces
Work directly with customers and internal stakeholders to align on feature requirements, timing constraints, and delivery milestones
Review and guide RTL, testbenches, and verification plans to catch architectural issues before they become silicon problems
The Impact You Will Have
Your architecture decisions will define the performance ceiling and power floor for memory IP used in next-generation AI and data center chips
You will reduce time-to-market by building memory controllers that are easier to verify, integrate, and customize across multiple product variants
The IP you help design will ship in millions of devices, from smartphones to high-performance computing systems
You will elevate the technical depth of the team by mentoring engineers and establishing architectural patterns that scale
Your ability to navigate ambiguity and make sound tradeoffs will directly influence which features ship and which get deferred
You will help Synopsys maintain its leadership position in memory IP by driving innovations in HBM3, DDR5, LPDDR5X, and beyond
The methodologies and design frameworks you put in place will improve quality and productivity across future memory IP projects
What You'll Need
12 - 15+ years of hands-on experience in ASIC digital design, with significant time spent on memory interfaces or high-speed IO protocols
Deep technical knowledge of at least one of HBM, DDR, LPDDR, or similar memory protocols, including controller architecture, training, and PHY interface
Proven ability to define and execute complex digital architectures from concept through RTL implementation and silicon bring-up
Strong understanding of AMBA or similar on-chip interconnect protocols and how memory controllers integrate into SoC architectures
Experience with advanced digital design tools and methodologies, including synthesis, timing closure, and low-power design techniques
Excellent communication skills, you can explain a complex architectural tradeoff to a product manager, a verification lead, and a customer engineer without losing clarity
Experience with HBM3, DDR5, or LPDDR5X is a strong plus
Who You Are
You can walk into a whiteboard session with incomplete requirements and walk out with a block diagram that the team can build from
When an RTL review surfaces a potential issue, you do not defend the design, you ask the right questions and figure out if it is real
You have a point of view on what good architecture looks like, and you are comfortable pushing back when a feature request does not make sense
You think about verification complexity while you are designing, not after the RTL is done
You are comfortable working across time zones with teams in the US, Europe, and Asia, and you know how to keep a distributed team aligned
You do not need to be the one writing every line of RTL, but you can drop into the code and debug a corner case when it matters
The Team You'll Be Part Of
You will join a dynamic and focused team advancing Synopsys' memory interface IP portfolio. The team works on HBM, DDR, and LPDDR digital core protocols, collaborating closely with PHY, verification, and product teams across global sites. You will be a key technical contributor to the architecture and execution of one of these memory protocols, helping define what the next generation of memory IP looks like. The team values technical depth, clear communication, and the ability to solve hard problems without perfect information.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
