What You'll Be Doing
Support pre-sales and post-sales engagements with semiconductor customers, demonstrating Synopsys physical design tools including Fusion Compiler and ICC2 in live technical sessions
Debug complex physical design issues across the RTL-to-GDSII flow, working directly with customer design teams to resolve placement, routing, timing closure, and congestion challenges at advanced nodes
Develop and deliver technical methodologies for clock tree synthesis, AI-driven optimization, macro placement, and timing closure that customers can adopt in production flows
Build proof-of-concept designs and benchmarks that show measurable PPA improvements using Synopsys tools compared to customer baseline flows
Collaborate with product engineering teams to translate customer pain points into feature requests, tool enhancements, and methodology improvements
Train customer engineers on advanced Synopsys tool capabilities, from multi-scenario optimization to noise-aware routing techniques
Travel to customer sites to provide hands-on technical support during critical project phases, including tape-out preparation and bring-up
The Impact You Will Have
Accelerate customer adoption of Synopsys tools, directly contributing to revenue growth and competitive wins in key accounts
Help customers achieve measurable improvements in PPA (power, performance, area) and reduce their time to tape-out by weeks or months through better methodologies
Influence the product roadmap by surfacing real-world customer challenges that shape the next generation of Fusion Compiler and ICC2 capabilities
Build long-term technical relationships with leading semiconductor companies, becoming the trusted expert they call when a design is stuck
Enable customers to successfully adopt advanced node technologies (5nm, 3nm, and beyond) where traditional methodologies break down
Expand Synopsys footprint within accounts by demonstrating value across multiple design teams and product lines
Contribute to the technical reputation of Synopsys in the industry through customer success stories, white papers, and conference presentations
What You'll Need
Bachelor's degree in Electrical Engineering or equivalent with 9+ years of hands-on ASIC physical design experience, or Master's degree with 7+ years
Deep expertise in RTL-to-GDSII flows using industry-standard tools, with direct experience in placement, optimization, clock tree synthesis, and routing
Hands-on proficiency with Synopsys backend tools including Fusion Compiler, ICC2, Design Compiler, and PrimeTime
Strong understanding of advanced node design challenges (7nm and below), including FinFET effects, multi-patterning constraints, and electromigration
Experience with timing closure techniques, multi-scenario optimization, and noise analysis in complex SoC designs
Knowledge of clock tree synthesis methodologies including H-Tree and multi-source CTS is a strong plus
Willingness to travel up to 30% to customer sites for technical engagements and on-site support
Who You Are
You can walk into a room where a customer's design is failing timing by 500ps and within an hour identify whether it is a methodology problem, a constraint problem, or a fundamental architecture issue
You communicate complex technical tradeoffs clearly, whether you are presenting to a staff engineer debugging a routing issue or a director deciding between tool vendors
You stay calm under pressure, especially when a customer is three weeks from tape-out and needs answers today, not next week
You are curious about why things break, not just how to fix them, and that curiosity makes you better at preventing problems upstream
You balance customer advocacy with product reality, pushing back when a request does not make sense but fighting hard when it does
You enjoy teaching, whether it is walking a junior engineer through CTS fundamentals or showing a principal engineer a technique they have not tried before
The Team You'll Be Part Of
You will join the Customer Success Group, the team responsible for helping the world's leading semiconductor companies design and verify advanced silicon chips. This is a technical sales enablement role, which means you will work closely with account teams, product engineers, and directly with customer design teams. The role is based in Sunnyvale, CA, with occasional travel.
