At Synopsys, you will work on Multi-Gbps SERDES IP that goes into chips that power data centers, automotive networks, and AI accelerators. The problems are hard, the process nodes are cutting-edge, and what you design will ship.
What You'll Be Doing
Review high-speed SerDes standards (PCIe, Ethernet, USB, CXL) and translate them into transceiver architectures and detailed sub-block specifications for Multi-Gbps NRZ and PAM4 designs
Architect and design analog/mixed-signal circuits including TX drivers, RX front-ends, adaptive equalizers, PLLs, DLLs, bandgap references, regulators, oscillators, and ADC/DAC blocks for advanced FinFET and gate-all-around process nodes
Collaborate with digital design teams on analog/digital co-design, calibration loops, adaptation algorithms, and timing handoff to ensure seamless integration and optimal performance
Work directly with layout engineers to guide physical implementation, minimize parasitics, manage device stress and process variation, and ensure robust post-silicon performance
Present simulation results, design trade-offs, and architectural decisions in internal reviews, customer meetings, and industry panel discussions
Document design features, simulation methodologies, test plans, and characterization results, and support post-silicon bring-up and debug with electrical analysis and design iteration proposals
Analyze customer silicon data and field performance to identify improvement opportunities and drive post-silicon design updates for next-generation IP releases
The Impact You Will Have
Define the architectural direction for Synopsys SERDES IP, influencing product roadmaps and enabling next-generation connectivity standards across automotive, data center, and AI markets
Deliver power, performance, and area improvements that directly affect the competitiveness of Synopsys IP in advanced process nodes and high-speed communication applications
Solve post-silicon challenges that unblock customer tape-outs and ensure successful deployment of Synopsys IP in high-volume production chips
Mentor analog designers across the team, raising the technical bar for circuit design, simulation methodology, and design-for-reliability practices
Strengthen Synopsys leadership in Multi-Gbps SERDES by contributing to industry standards bodies, customer engagements, and technical publications
Enable faster time-to-market for customers by streamlining design and verification flows and reducing silicon respins through robust pre-silicon validation
Shape the future of high-speed analog design at Synopsys by driving innovation in adaptive equalization, low-power PLLs, and signal integrity for next-generation process technologies
What You'll Need
MTech/MS with 8+ years or BTech/BS with 10+ years of hands-on analog IC design experience in Electrical Engineering, Computer Engineering, or a related field
Proven track record of CMOS tape-outs in FinFET technologies with demonstrable experience in Multi-Gbps high-speed designs using NRZ and PAM4 modulation
Deep expertise in SERDES sub-circuit design including TX drivers, RX front-ends, adaptive equalizers, PLLs, DLLs, bandgap references, regulators, oscillators, and data converters
Strong understanding of analog/digital co-design, calibration and adaptation algorithms, and timing handoff between analog and digital domains
Proficiency with schematic entry, physical layout collaboration, design verification tools, and SPICE simulators (Spectre, HSPICE, or similar)
Experience with scripting languages such as TCL, PERL, or MATLAB for post-processing simulation data and automating design tasks
Solid grounding in system-level budgeting for jitter, amplitude, and noise, and familiarity with signal integrity challenges including packaging parasitics, crosstalk, and channel loss. Experience with ESD protection, custom digital design, and design-for-reliability considerations (electromigration, IR drop, aging, self-heating) is a plus. Prior experience with high-speed interleaved SAR ADCs is a strong plus.
Who You Are
You can walk into a design review, look at a jitter waterfall plot, and pinpoint the architectural bottleneck in under five minutes without needing a slide deck
You push back when a specification does not make sense or when a layout decision will compromise performance, and you do it with data and a proposed alternative
You are the engineer others come to when a circuit is not behaving and simulation does not match silicon, because you know how to debug across domains and find the real root cause
You write clear, thorough documentation because you know that six months from now, someone else will need to understand your design choices and you want them to succeed
You stay current with emerging process technologies, circuit techniques, and industry standards because you know that what works in 7nm will not necessarily work in 3nm
You value collaboration and knowledge-sharing, and you take the time to explain a complex trade-off to a junior engineer or a non-technical stakeholder without losing the nuance
The Team You'll Be Part Of
Your recruiter will share more about the team structure and mission during the interview process.
Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
